76 	nvkm_wr32(device, 0x002600 + (chan->id * 4), chan->ramfc->addr >> 12);  in nv50_chan_bind()
86 	ret = nvkm_gpuobj_new(device, 0x0200, 0x1000, true, chan->inst, &chan->ramfc);  in nv50_chan_ramfc_write()
102 	nvkm_kmap(chan->ramfc);  in nv50_chan_ramfc_write()
103 	nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078);  in nv50_chan_ramfc_write()
104 	nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);  in nv50_chan_ramfc_write()
105 	nvkm_wo32(chan->ramfc, 0x48, chan->push->node->offset >> 4);  in nv50_chan_ramfc_write()
106 	nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(offset));  in nv50_chan_ramfc_write()
107 	nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(offset) | (limit2 << 16));  in nv50_chan_ramfc_write()
108 	nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);  in nv50_chan_ramfc_write()
109 	nvkm_wo32(chan->ramfc, 0x78, 0x00000000);  in nv50_chan_ramfc_write()
110 	nvkm_wo32(chan->ramfc, 0x7c, 0x30000000 | devm);  in nv50_chan_ramfc_write()
111 	nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |  in nv50_chan_ramfc_write()
114 	nvkm_done(chan->ramfc);  in nv50_chan_ramfc_write()
142 	.ramfc = &nv50_chan_ramfc,