219 			 struct hdmi_8996_phy_pll_reg_cfg *cfg)  in pll_calculate()  argument
286 		cfg->com_svs_mode_clk_sel = 1;  in pll_calculate()
288 		cfg->com_svs_mode_clk_sel = 2;  in pll_calculate()
290 	cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel);  in pll_calculate()
291 	cfg->com_pll_cctrl_mode0 = cctrl;  in pll_calculate()
292 	cfg->com_pll_rctrl_mode0 = rctrl;  in pll_calculate()
293 	cfg->com_cp_ctrl_mode0 = cpctrl;  in pll_calculate()
294 	cfg->com_dec_start_mode0 = dec_start;  in pll_calculate()
295 	cfg->com_div_frac_start1_mode0 = (frac_start & 0xff);  in pll_calculate()
296 	cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8);  in pll_calculate()
297 	cfg->com_div_frac_start3_mode0 = ((frac_start & 0xf0000) >> 16);  in pll_calculate()
298 	cfg->com_integloop_gain0_mode0 = (integloop_gain & 0xff);  in pll_calculate()
299 	cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xf00) >> 8);  in pll_calculate()
300 	cfg->com_lock_cmp1_mode0 = (pll_cmp & 0xff);  in pll_calculate()
301 	cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0xff00) >> 8);  in pll_calculate()
302 	cfg->com_lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16);  in pll_calculate()
303 	cfg->com_lock_cmp_en = 0x0;  in pll_calculate()
304 	cfg->com_core_clk_en = 0x2c;  in pll_calculate()
305 	cfg->com_coreclk_div = HDMI_CORECLK_DIV;  in pll_calculate()
306 	cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0;  in pll_calculate()
307 	cfg->com_vco_tune_ctrl = 0x0;  in pll_calculate()
309 	cfg->tx_lx_lane_mode[0] =  in pll_calculate()
310 		cfg->tx_lx_lane_mode[2] = 0x43;  in pll_calculate()
312 	cfg->tx_lx_hp_pd_enables[0] =  in pll_calculate()
313 		cfg->tx_lx_hp_pd_enables[1] =  in pll_calculate()
314 		cfg->tx_lx_hp_pd_enables[2] = 0x0c;  in pll_calculate()
315 	cfg->tx_lx_hp_pd_enables[3] = 0x3;  in pll_calculate()
318 		cfg->tx_lx_tx_band[i] = pd.tx_band_sel + 4;  in pll_calculate()
321 		cfg->tx_lx_tx_drv_lvl[0] =  in pll_calculate()
322 			cfg->tx_lx_tx_drv_lvl[1] =  in pll_calculate()
323 			cfg->tx_lx_tx_drv_lvl[2] = 0x25;  in pll_calculate()
324 		cfg->tx_lx_tx_drv_lvl[3] = 0x22;  in pll_calculate()
326 		cfg->tx_lx_tx_emp_post1_lvl[0] =  in pll_calculate()
327 			cfg->tx_lx_tx_emp_post1_lvl[1] =  in pll_calculate()
328 			cfg->tx_lx_tx_emp_post1_lvl[2] = 0x23;  in pll_calculate()
329 		cfg->tx_lx_tx_emp_post1_lvl[3] = 0x27;  in pll_calculate()
331 		cfg->tx_lx_vmode_ctrl1[0] =  in pll_calculate()
332 			cfg->tx_lx_vmode_ctrl1[1] =  in pll_calculate()
333 			cfg->tx_lx_vmode_ctrl1[2] =  in pll_calculate()
334 			cfg->tx_lx_vmode_ctrl1[3] = 0x00;  in pll_calculate()
336 		cfg->tx_lx_vmode_ctrl2[0] =  in pll_calculate()
337 			cfg->tx_lx_vmode_ctrl2[1] =  in pll_calculate()
338 			cfg->tx_lx_vmode_ctrl2[2] = 0x0D;  in pll_calculate()
340 		cfg->tx_lx_vmode_ctrl2[3] = 0x00;  in pll_calculate()
343 			cfg->tx_lx_tx_drv_lvl[i] = 0x25;  in pll_calculate()
344 			cfg->tx_lx_tx_emp_post1_lvl[i] = 0x23;  in pll_calculate()
345 			cfg->tx_lx_vmode_ctrl1[i] = 0x00;  in pll_calculate()
348 		cfg->tx_lx_vmode_ctrl2[0] =  in pll_calculate()
349 			cfg->tx_lx_vmode_ctrl2[1] =  in pll_calculate()
350 			cfg->tx_lx_vmode_ctrl2[2] = 0x0D;  in pll_calculate()
351 		cfg->tx_lx_vmode_ctrl2[3] = 0x00;  in pll_calculate()
354 			cfg->tx_lx_tx_drv_lvl[i] = 0x20;  in pll_calculate()
355 			cfg->tx_lx_tx_emp_post1_lvl[i] = 0x20;  in pll_calculate()
356 			cfg->tx_lx_vmode_ctrl1[i] = 0x00;  in pll_calculate()
357 			cfg->tx_lx_vmode_ctrl2[i] = 0x0E;  in pll_calculate()
361 	DBG("com_svs_mode_clk_sel = 0x%x", cfg->com_svs_mode_clk_sel);  in pll_calculate()
362 	DBG("com_hsclk_sel = 0x%x", cfg->com_hsclk_sel);  in pll_calculate()
363 	DBG("com_lock_cmp_en = 0x%x", cfg->com_lock_cmp_en);  in pll_calculate()
364 	DBG("com_pll_cctrl_mode0 = 0x%x", cfg->com_pll_cctrl_mode0);  in pll_calculate()
365 	DBG("com_pll_rctrl_mode0 = 0x%x", cfg->com_pll_rctrl_mode0);  in pll_calculate()
366 	DBG("com_cp_ctrl_mode0 = 0x%x", cfg->com_cp_ctrl_mode0);  in pll_calculate()
367 	DBG("com_dec_start_mode0 = 0x%x", cfg->com_dec_start_mode0);  in pll_calculate()
368 	DBG("com_div_frac_start1_mode0 = 0x%x", cfg->com_div_frac_start1_mode0);  in pll_calculate()
369 	DBG("com_div_frac_start2_mode0 = 0x%x", cfg->com_div_frac_start2_mode0);  in pll_calculate()
370 	DBG("com_div_frac_start3_mode0 = 0x%x", cfg->com_div_frac_start3_mode0);  in pll_calculate()
371 	DBG("com_integloop_gain0_mode0 = 0x%x", cfg->com_integloop_gain0_mode0);  in pll_calculate()
372 	DBG("com_integloop_gain1_mode0 = 0x%x", cfg->com_integloop_gain1_mode0);  in pll_calculate()
373 	DBG("com_lock_cmp1_mode0 = 0x%x", cfg->com_lock_cmp1_mode0);  in pll_calculate()
374 	DBG("com_lock_cmp2_mode0 = 0x%x", cfg->com_lock_cmp2_mode0);  in pll_calculate()
375 	DBG("com_lock_cmp3_mode0 = 0x%x", cfg->com_lock_cmp3_mode0);  in pll_calculate()
376 	DBG("com_core_clk_en = 0x%x", cfg->com_core_clk_en);  in pll_calculate()
377 	DBG("com_coreclk_div = 0x%x", cfg->com_coreclk_div);  in pll_calculate()
378 	DBG("phy_mode = 0x%x", cfg->phy_mode);  in pll_calculate()
380 	DBG("tx_l0_lane_mode = 0x%x", cfg->tx_lx_lane_mode[0]);  in pll_calculate()
381 	DBG("tx_l2_lane_mode = 0x%x", cfg->tx_lx_lane_mode[2]);  in pll_calculate()
384 		DBG("tx_l%d_tx_band = 0x%x", i, cfg->tx_lx_tx_band[i]);  in pll_calculate()
385 		DBG("tx_l%d_tx_drv_lvl = 0x%x", i, cfg->tx_lx_tx_drv_lvl[i]);  in pll_calculate()
387 		    cfg->tx_lx_tx_emp_post1_lvl[i]);  in pll_calculate()
388 		DBG("tx_l%d_vmode_ctrl1 = 0x%x", i, cfg->tx_lx_vmode_ctrl1[i]);  in pll_calculate()
389 		DBG("tx_l%d_vmode_ctrl2 = 0x%x", i, cfg->tx_lx_vmode_ctrl2[i]);  in pll_calculate()
400 	struct hdmi_8996_phy_pll_reg_cfg cfg;  in hdmi_8996_pll_set_clk_rate()  local
403 	memset(&cfg, 0x00, sizeof(cfg));  in hdmi_8996_pll_set_clk_rate()
405 	ret = pll_calculate(rate, parent_rate, &cfg);  in hdmi_8996_pll_set_clk_rate()
430 				   cfg.tx_lx_tx_band[i]);  in hdmi_8996_pll_set_clk_rate()
437 			   cfg.tx_lx_lane_mode[0]);  in hdmi_8996_pll_set_clk_rate()
439 			   cfg.tx_lx_lane_mode[2]);  in hdmi_8996_pll_set_clk_rate()
449 		       cfg.com_svs_mode_clk_sel);  in hdmi_8996_pll_set_clk_rate()
454 		       cfg.com_vco_tune_ctrl);  in hdmi_8996_pll_set_clk_rate()
460 		       cfg.com_hsclk_sel);  in hdmi_8996_pll_set_clk_rate()
462 		       cfg.com_lock_cmp_en);  in hdmi_8996_pll_set_clk_rate()
465 		       cfg.com_pll_cctrl_mode0);  in hdmi_8996_pll_set_clk_rate()
467 		       cfg.com_pll_rctrl_mode0);  in hdmi_8996_pll_set_clk_rate()
469 		       cfg.com_cp_ctrl_mode0);  in hdmi_8996_pll_set_clk_rate()
471 		       cfg.com_dec_start_mode0);  in hdmi_8996_pll_set_clk_rate()
473 		       cfg.com_div_frac_start1_mode0);  in hdmi_8996_pll_set_clk_rate()
475 		       cfg.com_div_frac_start2_mode0);  in hdmi_8996_pll_set_clk_rate()
477 		       cfg.com_div_frac_start3_mode0);  in hdmi_8996_pll_set_clk_rate()
480 		       cfg.com_integloop_gain0_mode0);  in hdmi_8996_pll_set_clk_rate()
482 		       cfg.com_integloop_gain1_mode0);  in hdmi_8996_pll_set_clk_rate()
485 		       cfg.com_lock_cmp1_mode0);  in hdmi_8996_pll_set_clk_rate()
487 		       cfg.com_lock_cmp2_mode0);  in hdmi_8996_pll_set_clk_rate()
489 		       cfg.com_lock_cmp3_mode0);  in hdmi_8996_pll_set_clk_rate()
493 		       cfg.com_core_clk_en);  in hdmi_8996_pll_set_clk_rate()
495 		       cfg.com_coreclk_div);  in hdmi_8996_pll_set_clk_rate()
504 				   cfg.tx_lx_tx_drv_lvl[i]);  in hdmi_8996_pll_set_clk_rate()
507 				   cfg.tx_lx_tx_emp_post1_lvl[i]);  in hdmi_8996_pll_set_clk_rate()
510 				   cfg.tx_lx_vmode_ctrl1[i]);  in hdmi_8996_pll_set_clk_rate()
513 				   cfg.tx_lx_vmode_ctrl2[i]);  in hdmi_8996_pll_set_clk_rate()
528 				   cfg.tx_lx_hp_pd_enables[i]);  in hdmi_8996_pll_set_clk_rate()
531 	hdmi_phy_write(phy, REG_HDMI_8996_PHY_MODE, cfg.phy_mode);  in hdmi_8996_pll_set_clk_rate()