526 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)  in CP_LOAD_STATE_0_DST_OFF()  argument
528 	return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;  in CP_LOAD_STATE_0_DST_OFF()
532 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)  in CP_LOAD_STATE_0_STATE_SRC()  argument
534 	return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;  in CP_LOAD_STATE_0_STATE_SRC()
538 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)  in CP_LOAD_STATE_0_STATE_BLOCK()  argument
540 	return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;  in CP_LOAD_STATE_0_STATE_BLOCK()
544 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)  in CP_LOAD_STATE_0_NUM_UNIT()  argument
546 	return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;  in CP_LOAD_STATE_0_NUM_UNIT()
552 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)  in CP_LOAD_STATE_1_STATE_TYPE()  argument
554 	return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;  in CP_LOAD_STATE_1_STATE_TYPE()
558 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)  in CP_LOAD_STATE_1_EXT_SRC_ADDR()  argument
560 	return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;  in CP_LOAD_STATE_1_EXT_SRC_ADDR()
566 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)  in CP_LOAD_STATE4_0_DST_OFF()  argument
568 	return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;  in CP_LOAD_STATE4_0_DST_OFF()
572 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)  in CP_LOAD_STATE4_0_STATE_SRC()  argument
574 	return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;  in CP_LOAD_STATE4_0_STATE_SRC()
578 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)  in CP_LOAD_STATE4_0_STATE_BLOCK()  argument
580 	return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;  in CP_LOAD_STATE4_0_STATE_BLOCK()
584 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)  in CP_LOAD_STATE4_0_NUM_UNIT()  argument
586 	return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;  in CP_LOAD_STATE4_0_NUM_UNIT()
592 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)  in CP_LOAD_STATE4_1_STATE_TYPE()  argument
594 	return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;  in CP_LOAD_STATE4_1_STATE_TYPE()
598 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)  in CP_LOAD_STATE4_1_EXT_SRC_ADDR()  argument
600 	return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;  in CP_LOAD_STATE4_1_EXT_SRC_ADDR()
606 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)  in CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI()  argument
608 	return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;  in CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI()
614 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)  in CP_LOAD_STATE6_0_DST_OFF()  argument
616 	return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;  in CP_LOAD_STATE6_0_DST_OFF()
620 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)  in CP_LOAD_STATE6_0_STATE_TYPE()  argument
622 	return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;  in CP_LOAD_STATE6_0_STATE_TYPE()
626 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)  in CP_LOAD_STATE6_0_STATE_SRC()  argument
628 	return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;  in CP_LOAD_STATE6_0_STATE_SRC()
632 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)  in CP_LOAD_STATE6_0_STATE_BLOCK()  argument
634 	return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;  in CP_LOAD_STATE6_0_STATE_BLOCK()
638 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)  in CP_LOAD_STATE6_0_NUM_UNIT()  argument
640 	return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;  in CP_LOAD_STATE6_0_NUM_UNIT()
646 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)  in CP_LOAD_STATE6_1_EXT_SRC_ADDR()  argument
648 	return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;  in CP_LOAD_STATE6_1_EXT_SRC_ADDR()
654 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)  in CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI()  argument
656 	return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;  in CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI()
664 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)  in CP_DRAW_INDX_0_VIZ_QUERY()  argument
666 	return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;  in CP_DRAW_INDX_0_VIZ_QUERY()
672 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_1_PRIM_TYPE()  argument
674 	return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;  in CP_DRAW_INDX_1_PRIM_TYPE()
678 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_1_SOURCE_SELECT()  argument
680 	return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;  in CP_DRAW_INDX_1_SOURCE_SELECT()
684 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_1_VIS_CULL()  argument
686 	return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;  in CP_DRAW_INDX_1_VIS_CULL()
690 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)  in CP_DRAW_INDX_1_INDEX_SIZE()  argument
692 	return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;  in CP_DRAW_INDX_1_INDEX_SIZE()
699 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)  in CP_DRAW_INDX_1_NUM_INSTANCES()  argument
701 	return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;  in CP_DRAW_INDX_1_NUM_INSTANCES()
707 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)  in CP_DRAW_INDX_2_NUM_INDICES()  argument
709 	return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;  in CP_DRAW_INDX_2_NUM_INDICES()
715 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)  in CP_DRAW_INDX_3_INDX_BASE()  argument
717 	return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;  in CP_DRAW_INDX_3_INDX_BASE()
723 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)  in CP_DRAW_INDX_4_INDX_SIZE()  argument
725 	return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;  in CP_DRAW_INDX_4_INDX_SIZE()
731 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)  in CP_DRAW_INDX_2_0_VIZ_QUERY()  argument
733 	return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;  in CP_DRAW_INDX_2_0_VIZ_QUERY()
739 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_2_1_PRIM_TYPE()  argument
741 	return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;  in CP_DRAW_INDX_2_1_PRIM_TYPE()
745 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_2_1_SOURCE_SELECT()  argument
747 	return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;  in CP_DRAW_INDX_2_1_SOURCE_SELECT()
751 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_2_1_VIS_CULL()  argument
753 	return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;  in CP_DRAW_INDX_2_1_VIS_CULL()
757 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)  in CP_DRAW_INDX_2_1_INDEX_SIZE()  argument
759 	return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;  in CP_DRAW_INDX_2_1_INDEX_SIZE()
766 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)  in CP_DRAW_INDX_2_1_NUM_INSTANCES()  argument
768 	return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;  in CP_DRAW_INDX_2_1_NUM_INSTANCES()
774 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)  in CP_DRAW_INDX_2_2_NUM_INDICES()  argument
776 	return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;  in CP_DRAW_INDX_2_2_NUM_INDICES()
782 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_OFFSET_0_PRIM_TYPE()  argument
784 	return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;  in CP_DRAW_INDX_OFFSET_0_PRIM_TYPE()
788 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT()  argument
790 …return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT…  in CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT()
794 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_OFFSET_0_VIS_CULL()  argument
796 	return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;  in CP_DRAW_INDX_OFFSET_0_VIS_CULL()
800 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)  in CP_DRAW_INDX_OFFSET_0_INDEX_SIZE()  argument
802 	return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;  in CP_DRAW_INDX_OFFSET_0_INDEX_SIZE()
806 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)  in CP_DRAW_INDX_OFFSET_0_PATCH_TYPE()  argument
808 	return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK;  in CP_DRAW_INDX_OFFSET_0_PATCH_TYPE()
816 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)  in CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES()  argument
818 …return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES…  in CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES()
824 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)  in CP_DRAW_INDX_OFFSET_2_NUM_INDICES()  argument
826 …return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MA…  in CP_DRAW_INDX_OFFSET_2_NUM_INDICES()
832 static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)  in CP_DRAW_INDX_OFFSET_3_FIRST_INDX()  argument
834 	return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK;  in CP_DRAW_INDX_OFFSET_3_FIRST_INDX()
841 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)  in CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO()  argument
843 …return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__…  in CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO()
849 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)  in CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI()  argument
851 …return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__…  in CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI()
859 static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)  in CP_DRAW_INDX_OFFSET_6_MAX_INDICES()  argument
861 …return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MA…  in CP_DRAW_INDX_OFFSET_6_MAX_INDICES()
867 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)  in CP_DRAW_INDX_OFFSET_4_INDX_BASE()  argument
869 	return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;  in CP_DRAW_INDX_OFFSET_4_INDX_BASE()
875 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)  in CP_DRAW_INDX_OFFSET_5_INDX_SIZE()  argument
877 	return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;  in CP_DRAW_INDX_OFFSET_5_INDX_SIZE()
883 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)  in A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE()  argument
885 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MA…  in A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE()
889 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT()  argument
891 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SE…  in A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT()
895 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A4XX_CP_DRAW_INDIRECT_0_VIS_CULL()  argument
897 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;  in A4XX_CP_DRAW_INDIRECT_0_VIS_CULL()
901 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)  in A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE()  argument
903 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__…  in A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE()
907 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)  in A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE()  argument
909 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__…  in A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE()
918 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)  in A4XX_CP_DRAW_INDIRECT_1_INDIRECT()  argument
920 	return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;  in A4XX_CP_DRAW_INDIRECT_1_INDIRECT()
927 static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)  in A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO()  argument
929 …return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO…  in A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO()
935 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)  in A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI()  argument
937 …return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI…  in A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI()
945 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE()  argument
947 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRI…  in A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE()
951 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT()  argument
953 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0…  in A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT()
957 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL()  argument
959 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_…  in A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL()
963 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE()  argument
965 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_IN…  in A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE()
969 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE()  argument
971 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PA…  in A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE()
980 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)  in A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE()  argument
982 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_IND…  in A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE()
988 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)  in A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE()  argument
990 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_IND…  in A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE()
996 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)  in A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT()  argument
998 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDI…  in A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT()
1005 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO()  argument
1007 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_…  in A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO()
1013 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI()  argument
1015 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_…  in A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI()
1023 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES()  argument
1025 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_M…  in A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES()
1031 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO()  argument
1033 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_I…  in A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO()
1039 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI()  argument
1041 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_I…  in A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI()
1049 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE()  argument
1051 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_P…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE()
1055 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT()  argument
1057 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT()
1061 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL()  argument
1063 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VI…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL()
1067 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE()  argument
1069 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE()
1073 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE()  argument
1075 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_…  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE()
1083 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)  in A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE()  argument
1085 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCO…  in A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE()
1089 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)  in A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF()  argument
1091 …return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST…  in A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF()
1137 static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val)  in CP_DRAW_PRED_SET_0_SRC()  argument
1139 	return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK;  in CP_DRAW_PRED_SET_0_SRC()
1143 static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val)  in CP_DRAW_PRED_SET_0_TEST()  argument
1145 	return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK;  in CP_DRAW_PRED_SET_0_TEST()
1155 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)  in CP_SET_DRAW_STATE__0_COUNT()  argument
1157 	return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;  in CP_SET_DRAW_STATE__0_COUNT()
1168 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)  in CP_SET_DRAW_STATE__0_GROUP_ID()  argument
1170 	return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;  in CP_SET_DRAW_STATE__0_GROUP_ID()
1176 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)  in CP_SET_DRAW_STATE__1_ADDR_LO()  argument
1178 	return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;  in CP_SET_DRAW_STATE__1_ADDR_LO()
1184 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)  in CP_SET_DRAW_STATE__2_ADDR_HI()  argument
1186 	return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;  in CP_SET_DRAW_STATE__2_ADDR_HI()
1194 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)  in CP_SET_BIN_1_X1()  argument
1196 	return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;  in CP_SET_BIN_1_X1()
1200 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)  in CP_SET_BIN_1_Y1()  argument
1202 	return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;  in CP_SET_BIN_1_Y1()
1208 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)  in CP_SET_BIN_2_X2()  argument
1210 	return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;  in CP_SET_BIN_2_X2()
1214 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)  in CP_SET_BIN_2_Y2()  argument
1216 	return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;  in CP_SET_BIN_2_Y2()
1222 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)  in CP_SET_BIN_DATA_0_BIN_DATA_ADDR()  argument
1224 	return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;  in CP_SET_BIN_DATA_0_BIN_DATA_ADDR()
1230 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)  in CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS()  argument
1232 …return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__…  in CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS()
1238 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)  in CP_SET_BIN_DATA5_0_VSC_SIZE()  argument
1240 	return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;  in CP_SET_BIN_DATA5_0_VSC_SIZE()
1244 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)  in CP_SET_BIN_DATA5_0_VSC_N()  argument
1246 	return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;  in CP_SET_BIN_DATA5_0_VSC_N()
1252 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)  in CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO()  argument
1254 …return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO…  in CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO()
1260 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)  in CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI()  argument
1262 …return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI…  in CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI()
1268 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)  in CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO()  argument
1270 …return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDR…  in CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO()
1276 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)  in CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI()  argument
1278 …return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDR…  in CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI()
1284 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)  in CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO()  argument
1286 …return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO…  in CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO()
1292 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)  in CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI()  argument
1294 …return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI…  in CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI()
1304 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE()  argument
1306 …return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__…  in CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE()
1310 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_0_VSC_N()  argument
1312 	return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK;  in CP_SET_BIN_DATA5_OFFSET_0_VSC_N()
1318 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET()  argument
1320 …return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN…  in CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET()
1326 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET()  argument
1328 …return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN…  in CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET()
1334 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)  in CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET()  argument
1336 …return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BI…  in CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET()
1342 static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val)  in CP_REG_RMW_0_DST_REG()  argument
1344 	return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK;  in CP_REG_RMW_0_DST_REG()
1348 static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val)  in CP_REG_RMW_0_ROTATE()  argument
1350 	return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK;  in CP_REG_RMW_0_ROTATE()
1359 static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val)  in CP_REG_RMW_1_SRC0()  argument
1361 	return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK;  in CP_REG_RMW_1_SRC0()
1367 static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val)  in CP_REG_RMW_2_SRC1()  argument
1369 	return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK;  in CP_REG_RMW_2_SRC1()
1375 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)  in CP_REG_TO_MEM_0_REG()  argument
1377 	return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;  in CP_REG_TO_MEM_0_REG()
1381 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)  in CP_REG_TO_MEM_0_CNT()  argument
1383 	return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;  in CP_REG_TO_MEM_0_CNT()
1391 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)  in CP_REG_TO_MEM_1_DEST()  argument
1393 	return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;  in CP_REG_TO_MEM_1_DEST()
1399 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)  in CP_REG_TO_MEM_2_DEST_HI()  argument
1401 	return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;  in CP_REG_TO_MEM_2_DEST_HI()
1407 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_0_REG()  argument
1409 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK;  in CP_REG_TO_MEM_OFFSET_REG_0_REG()
1413 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_0_CNT()  argument
1415 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK;  in CP_REG_TO_MEM_OFFSET_REG_0_CNT()
1423 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_1_DEST()  argument
1425 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK;  in CP_REG_TO_MEM_OFFSET_REG_1_DEST()
1431 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI()  argument
1433 …return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__…  in CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI()
1439 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)  in CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0()  argument
1441 …return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__…  in CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0()
1448 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_0_REG()  argument
1450 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK;  in CP_REG_TO_MEM_OFFSET_MEM_0_REG()
1454 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_0_CNT()  argument
1456 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK;  in CP_REG_TO_MEM_OFFSET_MEM_0_CNT()
1464 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_1_DEST()  argument
1466 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK;  in CP_REG_TO_MEM_OFFSET_MEM_1_DEST()
1472 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI()  argument
1474 …return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__…  in CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI()
1480 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO()  argument
1482 …return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_…  in CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO()
1488 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)  in CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI()  argument
1490 …return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_…  in CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI()
1496 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)  in CP_MEM_TO_REG_0_REG()  argument
1498 	return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;  in CP_MEM_TO_REG_0_REG()
1502 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)  in CP_MEM_TO_REG_0_CNT()  argument
1504 	return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;  in CP_MEM_TO_REG_0_CNT()
1512 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)  in CP_MEM_TO_REG_1_SRC()  argument
1514 	return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;  in CP_MEM_TO_REG_1_SRC()
1520 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)  in CP_MEM_TO_REG_2_SRC_HI()  argument
1522 	return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;  in CP_MEM_TO_REG_2_SRC_HI()
1536 static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val)  in CP_MEMCPY_0_DWORDS()  argument
1538 	return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK;  in CP_MEMCPY_0_DWORDS()
1544 static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val)  in CP_MEMCPY_1_SRC_LO()  argument
1546 	return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK;  in CP_MEMCPY_1_SRC_LO()
1552 static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val)  in CP_MEMCPY_2_SRC_HI()  argument
1554 	return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK;  in CP_MEMCPY_2_SRC_HI()
1560 static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val)  in CP_MEMCPY_3_DST_LO()  argument
1562 	return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK;  in CP_MEMCPY_3_DST_LO()
1568 static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val)  in CP_MEMCPY_4_DST_HI()  argument
1570 	return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK;  in CP_MEMCPY_4_DST_HI()
1576 static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val)  in CP_REG_TO_SCRATCH_0_REG()  argument
1578 	return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK;  in CP_REG_TO_SCRATCH_0_REG()
1582 static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)  in CP_REG_TO_SCRATCH_0_SCRATCH()  argument
1584 	return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK;  in CP_REG_TO_SCRATCH_0_SCRATCH()
1588 static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val)  in CP_REG_TO_SCRATCH_0_CNT()  argument
1590 	return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK;  in CP_REG_TO_SCRATCH_0_CNT()
1596 static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val)  in CP_SCRATCH_TO_REG_0_REG()  argument
1598 	return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK;  in CP_SCRATCH_TO_REG_0_REG()
1603 static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)  in CP_SCRATCH_TO_REG_0_SCRATCH()  argument
1605 	return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK;  in CP_SCRATCH_TO_REG_0_SCRATCH()
1609 static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val)  in CP_SCRATCH_TO_REG_0_CNT()  argument
1611 	return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK;  in CP_SCRATCH_TO_REG_0_CNT()
1617 static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)  in CP_SCRATCH_WRITE_0_SCRATCH()  argument
1619 	return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK;  in CP_SCRATCH_WRITE_0_SCRATCH()
1625 static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val)  in CP_MEM_WRITE_0_ADDR_LO()  argument
1627 	return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK;  in CP_MEM_WRITE_0_ADDR_LO()
1633 static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val)  in CP_MEM_WRITE_1_ADDR_HI()  argument
1635 	return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK;  in CP_MEM_WRITE_1_ADDR_HI()
1641 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)  in CP_COND_WRITE_0_FUNCTION()  argument
1643 	return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;  in CP_COND_WRITE_0_FUNCTION()
1651 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)  in CP_COND_WRITE_1_POLL_ADDR()  argument
1653 	return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;  in CP_COND_WRITE_1_POLL_ADDR()
1659 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)  in CP_COND_WRITE_2_REF()  argument
1661 	return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;  in CP_COND_WRITE_2_REF()
1667 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)  in CP_COND_WRITE_3_MASK()  argument
1669 	return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;  in CP_COND_WRITE_3_MASK()
1675 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)  in CP_COND_WRITE_4_WRITE_ADDR()  argument
1677 	return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;  in CP_COND_WRITE_4_WRITE_ADDR()
1683 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)  in CP_COND_WRITE_5_WRITE_DATA()  argument
1685 	return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;  in CP_COND_WRITE_5_WRITE_DATA()
1691 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)  in CP_COND_WRITE5_0_FUNCTION()  argument
1693 	return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;  in CP_COND_WRITE5_0_FUNCTION()
1703 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)  in CP_COND_WRITE5_1_POLL_ADDR_LO()  argument
1705 	return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;  in CP_COND_WRITE5_1_POLL_ADDR_LO()
1711 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)  in CP_COND_WRITE5_2_POLL_ADDR_HI()  argument
1713 	return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;  in CP_COND_WRITE5_2_POLL_ADDR_HI()
1719 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)  in CP_COND_WRITE5_3_REF()  argument
1721 	return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;  in CP_COND_WRITE5_3_REF()
1727 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)  in CP_COND_WRITE5_4_MASK()  argument
1729 	return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;  in CP_COND_WRITE5_4_MASK()
1735 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)  in CP_COND_WRITE5_5_WRITE_ADDR_LO()  argument
1737 	return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;  in CP_COND_WRITE5_5_WRITE_ADDR_LO()
1743 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)  in CP_COND_WRITE5_6_WRITE_ADDR_HI()  argument
1745 	return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;  in CP_COND_WRITE5_6_WRITE_ADDR_HI()
1751 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)  in CP_COND_WRITE5_7_WRITE_DATA()  argument
1753 	return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;  in CP_COND_WRITE5_7_WRITE_DATA()
1759 static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)  in CP_WAIT_MEM_GTE_0_RESERVED()  argument
1761 	return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK;  in CP_WAIT_MEM_GTE_0_RESERVED()
1767 static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)  in CP_WAIT_MEM_GTE_1_POLL_ADDR_LO()  argument
1769 	return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK;  in CP_WAIT_MEM_GTE_1_POLL_ADDR_LO()
1775 static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)  in CP_WAIT_MEM_GTE_2_POLL_ADDR_HI()  argument
1777 	return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK;  in CP_WAIT_MEM_GTE_2_POLL_ADDR_HI()
1783 static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val)  in CP_WAIT_MEM_GTE_3_REF()  argument
1785 	return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK;  in CP_WAIT_MEM_GTE_3_REF()
1791 static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)  in CP_WAIT_REG_MEM_0_FUNCTION()  argument
1793 	return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK;  in CP_WAIT_REG_MEM_0_FUNCTION()
1803 static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)  in CP_WAIT_REG_MEM_1_POLL_ADDR_LO()  argument
1805 	return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK;  in CP_WAIT_REG_MEM_1_POLL_ADDR_LO()
1811 static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)  in CP_WAIT_REG_MEM_2_POLL_ADDR_HI()  argument
1813 	return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK;  in CP_WAIT_REG_MEM_2_POLL_ADDR_HI()
1819 static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val)  in CP_WAIT_REG_MEM_3_REF()  argument
1821 	return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK;  in CP_WAIT_REG_MEM_3_REF()
1827 static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val)  in CP_WAIT_REG_MEM_4_MASK()  argument
1829 	return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK;  in CP_WAIT_REG_MEM_4_MASK()
1835 static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)  in CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES()  argument
1837 …return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES…  in CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES()
1843 static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val)  in CP_WAIT_TWO_REGS_0_REG0()  argument
1845 	return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK;  in CP_WAIT_TWO_REGS_0_REG0()
1851 static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val)  in CP_WAIT_TWO_REGS_1_REG1()  argument
1853 	return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK;  in CP_WAIT_TWO_REGS_1_REG1()
1859 static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val)  in CP_WAIT_TWO_REGS_2_REF()  argument
1861 	return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK;  in CP_WAIT_TWO_REGS_2_REF()
1869 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)  in CP_DISPATCH_COMPUTE_1_X()  argument
1871 	return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;  in CP_DISPATCH_COMPUTE_1_X()
1877 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)  in CP_DISPATCH_COMPUTE_2_Y()  argument
1879 	return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;  in CP_DISPATCH_COMPUTE_2_Y()
1885 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)  in CP_DISPATCH_COMPUTE_3_Z()  argument
1887 	return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;  in CP_DISPATCH_COMPUTE_3_Z()
1893 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)  in CP_SET_RENDER_MODE_0_MODE()  argument
1895 	return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;  in CP_SET_RENDER_MODE_0_MODE()
1901 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)  in CP_SET_RENDER_MODE_1_ADDR_0_LO()  argument
1903 	return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;  in CP_SET_RENDER_MODE_1_ADDR_0_LO()
1909 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)  in CP_SET_RENDER_MODE_2_ADDR_0_HI()  argument
1911 	return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;  in CP_SET_RENDER_MODE_2_ADDR_0_HI()
1923 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)  in CP_SET_RENDER_MODE_5_ADDR_1_LEN()  argument
1925 	return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;  in CP_SET_RENDER_MODE_5_ADDR_1_LEN()
1931 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)  in CP_SET_RENDER_MODE_6_ADDR_1_LO()  argument
1933 	return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;  in CP_SET_RENDER_MODE_6_ADDR_1_LO()
1939 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)  in CP_SET_RENDER_MODE_7_ADDR_1_HI()  argument
1941 	return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;  in CP_SET_RENDER_MODE_7_ADDR_1_HI()
1947 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)  in CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO()  argument
1949 …return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MA…  in CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO()
1955 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)  in CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI()  argument
1957 …return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MA…  in CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI()
1965 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)  in CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN()  argument
1967 …return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__…  in CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN()
1975 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)  in CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO()  argument
1977 …return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MA…  in CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO()
1983 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)  in CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI()  argument
1985 …return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MA…  in CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI()
1995 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)  in CP_PERFCOUNTER_ACTION_1_ADDR_0_LO()  argument
1997 …return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MA…  in CP_PERFCOUNTER_ACTION_1_ADDR_0_LO()
2003 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)  in CP_PERFCOUNTER_ACTION_2_ADDR_0_HI()  argument
2005 …return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MA…  in CP_PERFCOUNTER_ACTION_2_ADDR_0_HI()
2011 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)  in CP_EVENT_WRITE_0_EVENT()  argument
2013 	return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;  in CP_EVENT_WRITE_0_EVENT()
2021 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)  in CP_EVENT_WRITE_1_ADDR_0_LO()  argument
2023 	return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;  in CP_EVENT_WRITE_1_ADDR_0_LO()
2029 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)  in CP_EVENT_WRITE_2_ADDR_0_HI()  argument
2031 	return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;  in CP_EVENT_WRITE_2_ADDR_0_HI()
2039 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)  in CP_BLIT_0_OP()  argument
2041 	return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;  in CP_BLIT_0_OP()
2047 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)  in CP_BLIT_1_SRC_X1()  argument
2049 	return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;  in CP_BLIT_1_SRC_X1()
2053 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)  in CP_BLIT_1_SRC_Y1()  argument
2055 	return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;  in CP_BLIT_1_SRC_Y1()
2061 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)  in CP_BLIT_2_SRC_X2()  argument
2063 	return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;  in CP_BLIT_2_SRC_X2()
2067 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)  in CP_BLIT_2_SRC_Y2()  argument
2069 	return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;  in CP_BLIT_2_SRC_Y2()
2075 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)  in CP_BLIT_3_DST_X1()  argument
2077 	return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;  in CP_BLIT_3_DST_X1()
2081 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)  in CP_BLIT_3_DST_Y1()  argument
2083 	return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;  in CP_BLIT_3_DST_Y1()
2089 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)  in CP_BLIT_4_DST_X2()  argument
2091 	return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;  in CP_BLIT_4_DST_X2()
2095 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)  in CP_BLIT_4_DST_Y2()  argument
2097 	return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;  in CP_BLIT_4_DST_Y2()
2105 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)  in CP_EXEC_CS_1_NGROUPS_X()  argument
2107 	return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;  in CP_EXEC_CS_1_NGROUPS_X()
2113 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)  in CP_EXEC_CS_2_NGROUPS_Y()  argument
2115 	return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;  in CP_EXEC_CS_2_NGROUPS_Y()
2121 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)  in CP_EXEC_CS_3_NGROUPS_Z()  argument
2123 	return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;  in CP_EXEC_CS_3_NGROUPS_Z()
2132 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_1_ADDR()  argument
2134 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;  in A4XX_CP_EXEC_CS_INDIRECT_1_ADDR()
2140 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX()  argument
2142 …return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALS…  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX()
2146 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY()  argument
2148 …return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALS…  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY()
2152 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ()  argument
2154 …return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALS…  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ()
2161 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO()  argument
2163 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__…  in A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO()
2169 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI()  argument
2171 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__…  in A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI()
2177 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX()  argument
2179 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALS…  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX()
2183 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY()  argument
2185 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALS…  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY()
2189 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ()  argument
2191 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALS…  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ()
2197 static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val)  in A6XX_CP_SET_MARKER_0_MODE()  argument
2199 	return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK;  in A6XX_CP_SET_MARKER_0_MODE()
2203 static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val)  in A6XX_CP_SET_MARKER_0_MARKER()  argument
2205 	return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK;  in A6XX_CP_SET_MARKER_0_MARKER()
2213 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)  in A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG()  argument
2215 …return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_R…  in A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG()
2221 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)  in A6XX_CP_SET_PSEUDO_REG__1_LO()  argument
2223 	return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK;  in A6XX_CP_SET_PSEUDO_REG__1_LO()
2229 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)  in A6XX_CP_SET_PSEUDO_REG__2_HI()  argument
2231 	return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK;  in A6XX_CP_SET_PSEUDO_REG__2_HI()
2237 static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val)  in A6XX_CP_REG_TEST_0_REG()  argument
2239 	return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK;  in A6XX_CP_REG_TEST_0_REG()
2243 static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)  in A6XX_CP_REG_TEST_0_BIT()  argument
2245 	return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK;  in A6XX_CP_REG_TEST_0_BIT()
2250 static inline uint32_t A6XX_CP_REG_TEST_0_PRED_BIT(uint32_t val)  in A6XX_CP_REG_TEST_0_PRED_BIT()  argument
2252 	return ((val) << A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT) & A6XX_CP_REG_TEST_0_PRED_BIT__MASK;  in A6XX_CP_REG_TEST_0_PRED_BIT()
2263 static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val)  in CP_COND_REG_EXEC_0_REG0()  argument
2265 	return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK;  in CP_COND_REG_EXEC_0_REG0()
2269 static inline uint32_t CP_COND_REG_EXEC_0_PRED_BIT(uint32_t val)  in CP_COND_REG_EXEC_0_PRED_BIT()  argument
2271 	return ((val) << CP_COND_REG_EXEC_0_PRED_BIT__SHIFT) & CP_COND_REG_EXEC_0_PRED_BIT__MASK;  in CP_COND_REG_EXEC_0_PRED_BIT()
2278 static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)  in CP_COND_REG_EXEC_0_MODE()  argument
2280 	return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK;  in CP_COND_REG_EXEC_0_MODE()
2286 static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val)  in CP_COND_REG_EXEC_1_DWORDS()  argument
2288 	return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK;  in CP_COND_REG_EXEC_1_DWORDS()
2294 static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val)  in CP_COND_EXEC_0_ADDR0_LO()  argument
2296 	return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK;  in CP_COND_EXEC_0_ADDR0_LO()
2302 static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val)  in CP_COND_EXEC_1_ADDR0_HI()  argument
2304 	return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK;  in CP_COND_EXEC_1_ADDR0_HI()
2310 static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val)  in CP_COND_EXEC_2_ADDR1_LO()  argument
2312 	return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK;  in CP_COND_EXEC_2_ADDR1_LO()
2318 static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val)  in CP_COND_EXEC_3_ADDR1_HI()  argument
2320 	return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK;  in CP_COND_EXEC_3_ADDR1_HI()
2326 static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val)  in CP_COND_EXEC_4_REF()  argument
2328 	return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK;  in CP_COND_EXEC_4_REF()
2334 static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val)  in CP_COND_EXEC_5_DWORDS()  argument
2336 	return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK;  in CP_COND_EXEC_5_DWORDS()
2342 static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)  in CP_SET_CTXSWITCH_IB_0_ADDR_LO()  argument
2344 	return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK;  in CP_SET_CTXSWITCH_IB_0_ADDR_LO()
2350 static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)  in CP_SET_CTXSWITCH_IB_1_ADDR_HI()  argument
2352 	return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK;  in CP_SET_CTXSWITCH_IB_1_ADDR_HI()
2358 static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)  in CP_SET_CTXSWITCH_IB_2_DWORDS()  argument
2360 	return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK;  in CP_SET_CTXSWITCH_IB_2_DWORDS()
2364 static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)  in CP_SET_CTXSWITCH_IB_2_TYPE()  argument
2366 	return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK;  in CP_SET_CTXSWITCH_IB_2_TYPE()
2372 static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)  in CP_REG_WRITE_0_TRACKER()  argument
2374 	return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK;  in CP_REG_WRITE_0_TRACKER()
2384 static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)  in CP_SMMU_TABLE_UPDATE_0_TTBR0_LO()  argument
2386 	return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK;  in CP_SMMU_TABLE_UPDATE_0_TTBR0_LO()
2392 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)  in CP_SMMU_TABLE_UPDATE_1_TTBR0_HI()  argument
2394 	return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK;  in CP_SMMU_TABLE_UPDATE_1_TTBR0_HI()
2398 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)  in CP_SMMU_TABLE_UPDATE_1_ASID()  argument
2400 	return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK;  in CP_SMMU_TABLE_UPDATE_1_ASID()
2406 static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)  in CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR()  argument
2408 …return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MA…  in CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR()
2414 static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)  in CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK()  argument
2416 …return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__…  in CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK()
2436 static inline uint32_t CP_THREAD_CONTROL_0_THREAD(enum cp_thread val)  in CP_THREAD_CONTROL_0_THREAD()  argument
2438 	return ((val) << CP_THREAD_CONTROL_0_THREAD__SHIFT) & CP_THREAD_CONTROL_0_THREAD__MASK;  in CP_THREAD_CONTROL_0_THREAD()