Lines Matching refs:uint32_t

70 		uint32_t osd1_ctrl_stat;
71 		uint32_t osd1_ctrl_stat2;
72 		uint32_t osd1_blk0_cfg[5];
73 		uint32_t osd1_blk1_cfg4;
74 		uint32_t osd1_blk2_cfg4;
75 		uint32_t osd1_addr;
76 		uint32_t osd1_stride;
77 		uint32_t osd1_height;
78 		uint32_t osd1_width;
79 		uint32_t osd_sc_ctrl0;
80 		uint32_t osd_sc_i_wh_m1;
81 		uint32_t osd_sc_o_h_start_end;
82 		uint32_t osd_sc_o_v_start_end;
83 		uint32_t osd_sc_v_ini_phase;
84 		uint32_t osd_sc_v_phase_step;
85 		uint32_t osd_sc_h_ini_phase;
86 		uint32_t osd_sc_h_phase_step;
87 		uint32_t osd_sc_h_ctrl0;
88 		uint32_t osd_sc_v_ctrl0;
89 		uint32_t osd_blend_din0_scope_h;
90 		uint32_t osd_blend_din0_scope_v;
91 		uint32_t osb_blend0_size;
92 		uint32_t osb_blend1_size;
98 		uint32_t vd1_if0_gen_reg;
99 		uint32_t vd1_if0_luma_x0;
100 		uint32_t vd1_if0_luma_y0;
101 		uint32_t vd1_if0_chroma_x0;
102 		uint32_t vd1_if0_chroma_y0;
103 		uint32_t vd1_if0_repeat_loop;
104 		uint32_t vd1_if0_luma0_rpt_pat;
105 		uint32_t vd1_if0_chroma0_rpt_pat;
106 		uint32_t vd1_range_map_y;
107 		uint32_t vd1_range_map_cb;
108 		uint32_t vd1_range_map_cr;
109 		uint32_t viu_vd1_fmt_w;
110 		uint32_t vd1_if0_canvas0;
111 		uint32_t vd1_if0_gen_reg2;
112 		uint32_t viu_vd1_fmt_ctrl;
113 		uint32_t vd1_addr0;
114 		uint32_t vd1_addr1;
115 		uint32_t vd1_addr2;
116 		uint32_t vd1_stride0;
117 		uint32_t vd1_stride1;
118 		uint32_t vd1_stride2;
119 		uint32_t vd1_height0;
120 		uint32_t vd1_height1;
121 		uint32_t vd1_height2;
122 		uint32_t vd1_afbc_mode;
123 		uint32_t vd1_afbc_en;
124 		uint32_t vd1_afbc_head_addr;
125 		uint32_t vd1_afbc_body_addr;
126 		uint32_t vd1_afbc_conv_ctrl;
127 		uint32_t vd1_afbc_dec_def_color;
128 		uint32_t vd1_afbc_vd_cfmt_ctrl;
129 		uint32_t vd1_afbc_vd_cfmt_w;
130 		uint32_t vd1_afbc_vd_cfmt_h;
131 		uint32_t vd1_afbc_mif_hor_scope;
132 		uint32_t vd1_afbc_mif_ver_scope;
133 		uint32_t vd1_afbc_size_out;
134 		uint32_t vd1_afbc_pixel_hor_scope;
135 		uint32_t vd1_afbc_pixel_ver_scope;
136 		uint32_t vd1_afbc_size_in;
137 		uint32_t vpp_pic_in_height;
138 		uint32_t vpp_postblend_vd1_h_start_end;
139 		uint32_t vpp_postblend_vd1_v_start_end;
140 		uint32_t vpp_hsc_region12_startp;
141 		uint32_t vpp_hsc_region34_startp;
142 		uint32_t vpp_hsc_region4_endp;
143 		uint32_t vpp_hsc_start_phase_step;
144 		uint32_t vpp_hsc_region1_phase_slope;
145 		uint32_t vpp_hsc_region3_phase_slope;
146 		uint32_t vpp_line_in_length;
147 		uint32_t vpp_preblend_h_size;
148 		uint32_t vpp_vsc_region12_startp;
149 		uint32_t vpp_vsc_region34_startp;
150 		uint32_t vpp_vsc_region4_endp;
151 		uint32_t vpp_vsc_start_phase_step;
152 		uint32_t vpp_vsc_ini_phase;
153 		uint32_t vpp_vsc_phase_ctrl;
154 		uint32_t vpp_hsc_phase_ctrl;
155 		uint32_t vpp_blend_vd2_h_start_end;
156 		uint32_t vpp_blend_vd2_v_start_end;
168 		uint32_t *addr;