82 		    i915_reg_t iir, i915_reg_t ier)  in gen3_irq_reset()  argument
90 	intel_uncore_write(uncore, iir, 0xffffffff);  in gen3_irq_reset()
91 	intel_uncore_posting_read(uncore, iir);  in gen3_irq_reset()
92 	intel_uncore_write(uncore, iir, 0xffffffff);  in gen3_irq_reset()
93 	intel_uncore_posting_read(uncore, iir);  in gen3_irq_reset()
148 		   i915_reg_t iir)  in gen3_irq_init()  argument
150 	gen3_assert_iir_is_zero(uncore, iir);  in gen3_irq_init()
263 		u32 iir, gt_iir, pm_iir;  in valleyview_irq_handler()  local
270 		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);  in valleyview_irq_handler()
272 		if (gt_iir == 0 && pm_iir == 0 && iir == 0)  in valleyview_irq_handler()
298 		if (iir & I915_DISPLAY_PORT_INTERRUPT)  in valleyview_irq_handler()
303 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in valleyview_irq_handler()
305 		if (iir & (I915_LPE_PIPE_A_INTERRUPT |  in valleyview_irq_handler()
313 		if (iir)  in valleyview_irq_handler()
314 			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);  in valleyview_irq_handler()
349 		u32 master_ctl, iir;  in cherryview_irq_handler()  local
355 		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);  in cherryview_irq_handler()
357 		if (master_ctl == 0 && iir == 0)  in cherryview_irq_handler()
380 		if (iir & I915_DISPLAY_PORT_INTERRUPT)  in cherryview_irq_handler()
385 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in cherryview_irq_handler()
387 		if (iir & (I915_LPE_PIPE_A_INTERRUPT |  in cherryview_irq_handler()
396 		if (iir)  in cherryview_irq_handler()
397 			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);  in cherryview_irq_handler()
1002 		u16 iir;  in i8xx_irq_handler()  local
1004 		iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);  in i8xx_irq_handler()
1005 		if (iir == 0)  in i8xx_irq_handler()
1012 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in i8xx_irq_handler()
1014 		if (iir & I915_MASTER_ERROR_INTERRUPT)  in i8xx_irq_handler()
1017 		intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);  in i8xx_irq_handler()
1019 		if (iir & I915_USER_INTERRUPT)  in i8xx_irq_handler()
1020 			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);  in i8xx_irq_handler()
1022 		if (iir & I915_MASTER_ERROR_INTERRUPT)  in i8xx_irq_handler()
1025 		i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);  in i8xx_irq_handler()
1105 		u32 iir;  in i915_irq_handler()  local
1107 		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);  in i915_irq_handler()
1108 		if (iir == 0)  in i915_irq_handler()
1114 		    iir & I915_DISPLAY_PORT_INTERRUPT)  in i915_irq_handler()
1119 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in i915_irq_handler()
1121 		if (iir & I915_MASTER_ERROR_INTERRUPT)  in i915_irq_handler()
1124 		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);  in i915_irq_handler()
1126 		if (iir & I915_USER_INTERRUPT)  in i915_irq_handler()
1127 			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);  in i915_irq_handler()
1129 		if (iir & I915_MASTER_ERROR_INTERRUPT)  in i915_irq_handler()
1135 		i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);  in i915_irq_handler()
1231 		u32 iir;  in i965_irq_handler()  local
1233 		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);  in i965_irq_handler()
1234 		if (iir == 0)  in i965_irq_handler()
1239 		if (iir & I915_DISPLAY_PORT_INTERRUPT)  in i965_irq_handler()
1244 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);  in i965_irq_handler()
1246 		if (iir & I915_MASTER_ERROR_INTERRUPT)  in i965_irq_handler()
1249 		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);  in i965_irq_handler()
1251 		if (iir & I915_USER_INTERRUPT)  in i965_irq_handler()
1253 					    iir);  in i965_irq_handler()
1255 		if (iir & I915_BSD_USER_INTERRUPT)  in i965_irq_handler()
1257 					    iir >> 25);  in i965_irq_handler()
1259 		if (iir & I915_MASTER_ERROR_INTERRUPT)  in i965_irq_handler()
1265 		i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);  in i965_irq_handler()