48 #define get_event_virt_handler(irq, e)	(irq->events[e].v_handler)  argument
49 #define get_irq_info(irq, e)		(irq->events[e].info)  argument
51 #define irq_to_gvt(irq) \  argument
52 	container_of(irq, struct intel_gvt, irq)
153 	struct intel_gvt_irq *irq = &gvt->irq;  in regbase_to_irq_info()  local
156 	for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {  in regbase_to_irq_info()
157 		if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)  in regbase_to_irq_info()
158 			return irq->info[i];  in regbase_to_irq_info()
182 	const struct intel_gvt_irq_ops *ops = gvt->irq.ops;  in intel_vgpu_reg_imr_handler()
212 	const struct intel_gvt_irq_ops *ops = gvt->irq.ops;  in intel_vgpu_reg_master_irq_handler()
252 	const struct intel_gvt_irq_ops *ops = gvt->irq.ops;  in intel_vgpu_reg_ier_handler()
328 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;  in update_upstream_irq()  local
329 	struct intel_gvt_irq_map *map = irq->irq_map;  in update_upstream_irq()
342 	for (map = irq->irq_map; map->up_irq_bit != -1; map++) {  in update_upstream_irq()
347 			up_irq_info = irq->info[map->up_irq_group];  in update_upstream_irq()
350 				    irq->info[map->up_irq_group]);  in update_upstream_irq()
381 static void init_irq_map(struct intel_gvt_irq *irq)  in init_irq_map()  argument
387 	for (map = irq->irq_map; map->up_irq_bit != -1; map++) {  in init_irq_map()
388 		up_info = irq->info[map->up_irq_group];  in init_irq_map()
390 		down_info = irq->info[map->down_irq_group];  in init_irq_map()
443 static void propagate_event(struct intel_gvt_irq *irq,  in propagate_event()  argument
450 	info = get_irq_info(irq, event);  in propagate_event()
455 	bit = irq->events[event].bit;  in propagate_event()
466 static void handle_default_event_virt(struct intel_gvt_irq *irq,  in handle_default_event_virt()  argument
469 	if (!vgpu->irq.irq_warn_once[event]) {  in handle_default_event_virt()
472 		vgpu->irq.irq_warn_once[event] = true;  in handle_default_event_virt()
474 	propagate_event(irq, event, vgpu);  in handle_default_event_virt()
509 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;  in gen8_check_pending_irq()  local
516 	for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {  in gen8_check_pending_irq()
517 		struct intel_gvt_irq_info *info = irq->info[i];  in gen8_check_pending_irq()
535 		struct intel_gvt_irq *irq)  in gen8_init_irq()  argument
537 	struct intel_gvt *gvt = irq_to_gvt(irq);  in gen8_init_irq()
553 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info);  in gen8_init_irq()
554 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info);  in gen8_init_irq()
555 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info);  in gen8_init_irq()
556 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info);  in gen8_init_irq()
557 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info);  in gen8_init_irq()
558 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info);  in gen8_init_irq()
559 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info);  in gen8_init_irq()
560 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info);  in gen8_init_irq()
561 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info);  in gen8_init_irq()
562 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info);  in gen8_init_irq()
563 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info);  in gen8_init_irq()
564 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info);  in gen8_init_irq()
569 	SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);  in gen8_init_irq()
570 	SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0);  in gen8_init_irq()
571 	SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);  in gen8_init_irq()
573 	SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);  in gen8_init_irq()
574 	SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0);  in gen8_init_irq()
575 	SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);  in gen8_init_irq()
578 	SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1);  in gen8_init_irq()
579 	SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);  in gen8_init_irq()
580 	SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);  in gen8_init_irq()
583 		SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,  in gen8_init_irq()
585 		SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,  in gen8_init_irq()
587 		SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH,  in gen8_init_irq()
592 	SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3);  in gen8_init_irq()
593 	SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3);  in gen8_init_irq()
594 	SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3);  in gen8_init_irq()
596 	SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A);  in gen8_init_irq()
597 	SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B);  in gen8_init_irq()
598 	SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C);  in gen8_init_irq()
601 	SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT);  in gen8_init_irq()
602 	SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT);  in gen8_init_irq()
605 	SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC);  in gen8_init_irq()
608 	SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH);  in gen8_init_irq()
609 	SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);  in gen8_init_irq()
610 	SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);  in gen8_init_irq()
611 	SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);  in gen8_init_irq()
612 	SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);  in gen8_init_irq()
615 		SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);  in gen8_init_irq()
616 		SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);  in gen8_init_irq()
617 		SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);  in gen8_init_irq()
619 		SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);  in gen8_init_irq()
620 		SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);  in gen8_init_irq()
622 		SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);  in gen8_init_irq()
623 		SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);  in gen8_init_irq()
625 		SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);  in gen8_init_irq()
626 		SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);  in gen8_init_irq()
628 		SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);  in gen8_init_irq()
629 		SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);  in gen8_init_irq()
630 		SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);  in gen8_init_irq()
632 		SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);  in gen8_init_irq()
633 		SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);  in gen8_init_irq()
634 		SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);  in gen8_init_irq()
636 		SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);  in gen8_init_irq()
637 		SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);  in gen8_init_irq()
638 		SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);  in gen8_init_irq()
642 	SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU);  in gen8_init_irq()
643 	SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU);  in gen8_init_irq()
666 	struct intel_gvt_irq *irq = &gvt->irq;  in intel_vgpu_trigger_virtual_event()  local
668 	const struct intel_gvt_irq_ops *ops = gvt->irq.ops;  in intel_vgpu_trigger_virtual_event()
670 	handler = get_event_virt_handler(irq, event);  in intel_vgpu_trigger_virtual_event()
673 	handler(irq, event, vgpu);  in intel_vgpu_trigger_virtual_event()
679 	struct intel_gvt_irq *irq)  in init_events()  argument
684 		irq->events[i].info = NULL;  in init_events()
685 		irq->events[i].v_handler = handle_default_event_virt;  in init_events()
701 	struct intel_gvt_irq *irq = &gvt->irq;  in intel_gvt_init_irq()  local
705 	irq->ops = &gen8_irq_ops;  in intel_gvt_init_irq()
706 	irq->irq_map = gen8_irq_map;  in intel_gvt_init_irq()
709 	init_events(irq);  in intel_gvt_init_irq()
712 	irq->ops->init_irq(irq);  in intel_gvt_init_irq()
714 	init_irq_map(irq);  in intel_gvt_init_irq()