84 	u32 *cs;  in emit_semaphore_signal()  local
90 	cs = intel_ring_begin(rq, 4);  in emit_semaphore_signal()
91 	if (IS_ERR(cs)) {  in emit_semaphore_signal()
93 		return PTR_ERR(cs);  in emit_semaphore_signal()
96 	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;  in emit_semaphore_signal()
97 	*cs++ = offset;  in emit_semaphore_signal()
98 	*cs++ = 0;  in emit_semaphore_signal()
99 	*cs++ = 1;  in emit_semaphore_signal()
101 	intel_ring_advance(rq, cs);  in emit_semaphore_signal()
414 	u32 *cs;  in __live_lrc_state()  local
436 	cs = intel_ring_begin(rq, 4 * MAX_IDX);  in __live_lrc_state()
437 	if (IS_ERR(cs)) {  in __live_lrc_state()
438 		err = PTR_ERR(cs);  in __live_lrc_state()
443 	*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;  in __live_lrc_state()
444 	*cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base));  in __live_lrc_state()
445 	*cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32);  in __live_lrc_state()
446 	*cs++ = 0;  in __live_lrc_state()
450 	*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;  in __live_lrc_state()
451 	*cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base));  in __live_lrc_state()
452 	*cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);  in __live_lrc_state()
453 	*cs++ = 0;  in __live_lrc_state()
470 	cs = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);  in __live_lrc_state()
471 	if (IS_ERR(cs)) {  in __live_lrc_state()
472 		err = PTR_ERR(cs);  in __live_lrc_state()
477 		if (cs[n] != expected[n]) {  in __live_lrc_state()
479 			       engine->name, n, cs[n], expected[n]);  in __live_lrc_state()
535 	u32 *cs;  in gpr_make_dirty()  local
542 	cs = intel_ring_begin(rq, 2 * NUM_GPR_DW + 2);  in gpr_make_dirty()
543 	if (IS_ERR(cs)) {  in gpr_make_dirty()
545 		return PTR_ERR(cs);  in gpr_make_dirty()
548 	*cs++ = MI_LOAD_REGISTER_IMM(NUM_GPR_DW);  in gpr_make_dirty()
550 		*cs++ = CS_GPR(ce->engine, n);  in gpr_make_dirty()
551 		*cs++ = STACK_MAGIC;  in gpr_make_dirty()
553 	*cs++ = MI_NOOP;  in gpr_make_dirty()
555 	intel_ring_advance(rq, cs);  in gpr_make_dirty()
570 	u32 *cs;  in __gpr_read()  local
578 	cs = intel_ring_begin(rq, 6 + 4 * NUM_GPR_DW);  in __gpr_read()
579 	if (IS_ERR(cs)) {  in __gpr_read()
581 		return ERR_CAST(cs);  in __gpr_read()
584 	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;  in __gpr_read()
585 	*cs++ = MI_NOOP;  in __gpr_read()
587 	*cs++ = MI_SEMAPHORE_WAIT |  in __gpr_read()
591 	*cs++ = 0;  in __gpr_read()
592 	*cs++ = offset;  in __gpr_read()
593 	*cs++ = 0;  in __gpr_read()
596 		*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;  in __gpr_read()
597 		*cs++ = CS_GPR(ce->engine, n);  in __gpr_read()
598 		*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);  in __gpr_read()
599 		*cs++ = 0;  in __gpr_read()
621 	u32 *cs;  in __live_lrc_gpr()  local
668 	cs = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);  in __live_lrc_gpr()
669 	if (IS_ERR(cs)) {  in __live_lrc_gpr()
670 		err = PTR_ERR(cs);  in __live_lrc_gpr()
675 		if (cs[n]) {  in __live_lrc_gpr()
679 			       cs[n]);  in __live_lrc_gpr()
743 	u32 *cs;  in create_timestamp()  local
750 	cs = intel_ring_begin(rq, 10);  in create_timestamp()
751 	if (IS_ERR(cs)) {  in create_timestamp()
752 		err = PTR_ERR(cs);  in create_timestamp()
756 	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;  in create_timestamp()
757 	*cs++ = MI_NOOP;  in create_timestamp()
759 	*cs++ = MI_SEMAPHORE_WAIT |  in create_timestamp()
763 	*cs++ = 0;  in create_timestamp()
764 	*cs++ = offset;  in create_timestamp()
765 	*cs++ = 0;  in create_timestamp()
767 	*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;  in create_timestamp()
768 	*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(rq->engine->mmio_base));  in create_timestamp()
769 	*cs++ = offset + idx * sizeof(u32);  in create_timestamp()
770 	*cs++ = 0;  in create_timestamp()
772 	intel_ring_advance(rq, cs);  in create_timestamp()
967 	u32 dw, x, *cs, *hw;  in store_context()  local
974 	cs = i915_gem_object_pin_map_unlocked(batch->obj, I915_MAP_WC);  in store_context()
975 	if (IS_ERR(cs)) {  in store_context()
977 		return ERR_CAST(cs);  in store_context()
1029 			*cs++ = MI_STORE_REGISTER_MEM_GEN8;  in store_context()
1030 			*cs++ = hw[dw];  in store_context()
1031 			*cs++ = lower_32_bits(i915_vma_offset(scratch) + x);  in store_context()
1032 			*cs++ = upper_32_bits(i915_vma_offset(scratch) + x);  in store_context()
1040 	*cs++ = MI_BATCH_BUFFER_END;  in store_context()
1058 	u32 *cs;  in record_registers()  local
1091 	cs = intel_ring_begin(rq, 14);  in record_registers()
1092 	if (IS_ERR(cs)) {  in record_registers()
1093 		err = PTR_ERR(cs);  in record_registers()
1097 	*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;  in record_registers()
1098 	*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);  in record_registers()
1099 	*cs++ = lower_32_bits(i915_vma_offset(b_before));  in record_registers()
1100 	*cs++ = upper_32_bits(i915_vma_offset(b_before));  in record_registers()
1102 	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;  in record_registers()
1103 	*cs++ = MI_SEMAPHORE_WAIT |  in record_registers()
1107 	*cs++ = 0;  in record_registers()
1108 	*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +  in record_registers()
1110 	*cs++ = 0;  in record_registers()
1111 	*cs++ = MI_NOOP;  in record_registers()
1113 	*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;  in record_registers()
1114 	*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);  in record_registers()
1115 	*cs++ = lower_32_bits(i915_vma_offset(b_after));  in record_registers()
1116 	*cs++ = upper_32_bits(i915_vma_offset(b_after));  in record_registers()
1118 	intel_ring_advance(rq, cs);  in record_registers()
1138 	u32 dw, *cs, *hw;  in load_context()  local
1145 	cs = i915_gem_object_pin_map_unlocked(batch->obj, I915_MAP_WC);  in load_context()
1146 	if (IS_ERR(cs)) {  in load_context()
1148 		return ERR_CAST(cs);  in load_context()
1187 		*cs++ = MI_LOAD_REGISTER_IMM(len);  in load_context()
1189 			*cs++ = hw[dw];  in load_context()
1190 			*cs++ = safe_poison(hw[dw] & get_lri_mask(ce->engine,  in load_context()
1198 	*cs++ = MI_BATCH_BUFFER_END;  in load_context()
1212 	u32 *cs;  in poison_registers()  local
1229 	cs = intel_ring_begin(rq, 8);  in poison_registers()
1230 	if (IS_ERR(cs)) {  in poison_registers()
1231 		err = PTR_ERR(cs);  in poison_registers()
1235 	*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;  in poison_registers()
1236 	*cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);  in poison_registers()
1237 	*cs++ = lower_32_bits(i915_vma_offset(batch));  in poison_registers()
1238 	*cs++ = upper_32_bits(i915_vma_offset(batch));  in poison_registers()
1240 	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;  in poison_registers()
1241 	*cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +  in poison_registers()
1243 	*cs++ = 0;  in poison_registers()
1244 	*cs++ = 1;  in poison_registers()
1246 	intel_ring_advance(rq, cs);  in poison_registers()
1582 emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs)  in emit_indirect_ctx_bb_canary()  argument
1584 	*cs++ = MI_STORE_REGISTER_MEM_GEN8 |  in emit_indirect_ctx_bb_canary()
1587 	*cs++ = i915_mmio_reg_offset(RING_START(0));  in emit_indirect_ctx_bb_canary()
1588 	*cs++ = i915_ggtt_offset(ce->state) +  in emit_indirect_ctx_bb_canary()
1591 	*cs++ = 0;  in emit_indirect_ctx_bb_canary()
1593 	return cs;  in emit_indirect_ctx_bb_canary()
1599 	u32 *cs = context_indirect_bb(ce);  in indirect_ctx_bb_setup()  local
1601 	cs[CTX_BB_CANARY_INDEX] = 0xdeadf00d;  in indirect_ctx_bb_setup()