1576 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)  in gen8_emit_flush_coherentl3_wa()  argument
1579 	*batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;  in gen8_emit_flush_coherentl3_wa()
1580 	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);  in gen8_emit_flush_coherentl3_wa()
1581 	*batch++ = intel_gt_scratch_offset(engine->gt,  in gen8_emit_flush_coherentl3_wa()
1583 	*batch++ = 0;  in gen8_emit_flush_coherentl3_wa()
1585 	*batch++ = MI_LOAD_REGISTER_IMM(1);  in gen8_emit_flush_coherentl3_wa()
1586 	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);  in gen8_emit_flush_coherentl3_wa()
1587 	*batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;  in gen8_emit_flush_coherentl3_wa()
1589 	batch = gen8_emit_pipe_control(batch,  in gen8_emit_flush_coherentl3_wa()
1594 	*batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;  in gen8_emit_flush_coherentl3_wa()
1595 	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);  in gen8_emit_flush_coherentl3_wa()
1596 	*batch++ = intel_gt_scratch_offset(engine->gt,  in gen8_emit_flush_coherentl3_wa()
1598 	*batch++ = 0;  in gen8_emit_flush_coherentl3_wa()
1600 	return batch;  in gen8_emit_flush_coherentl3_wa()
1618 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)  in gen8_init_indirectctx_bb()  argument
1621 	*batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;  in gen8_init_indirectctx_bb()
1625 		batch = gen8_emit_flush_coherentl3_wa(engine, batch);  in gen8_init_indirectctx_bb()
1629 	batch = gen8_emit_pipe_control(batch,  in gen8_init_indirectctx_bb()
1636 	*batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;  in gen8_init_indirectctx_bb()
1639 	while ((unsigned long)batch % CACHELINE_BYTES)  in gen8_init_indirectctx_bb()
1640 		*batch++ = MI_NOOP;  in gen8_init_indirectctx_bb()
1648 	return batch;  in gen8_init_indirectctx_bb()
1656 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)  in emit_lri()  argument
1660 	*batch++ = MI_LOAD_REGISTER_IMM(count);  in emit_lri()
1662 		*batch++ = i915_mmio_reg_offset(lri->reg);  in emit_lri()
1663 		*batch++ = lri->value;  in emit_lri()
1665 	*batch++ = MI_NOOP;  in emit_lri()
1667 	return batch;  in emit_lri()
1670 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)  in gen9_init_indirectctx_bb()  argument
1695 	*batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;  in gen9_init_indirectctx_bb()
1698 	batch = gen8_emit_flush_coherentl3_wa(engine, batch);  in gen9_init_indirectctx_bb()
1701 	batch = gen8_emit_pipe_control(batch,  in gen9_init_indirectctx_bb()
1708 	batch = emit_lri(batch, lri, ARRAY_SIZE(lri));  in gen9_init_indirectctx_bb()
1725 		*batch++ = GEN9_MEDIA_POOL_STATE;  in gen9_init_indirectctx_bb()
1726 		*batch++ = GEN9_MEDIA_POOL_ENABLE;  in gen9_init_indirectctx_bb()
1727 		*batch++ = 0x00777000;  in gen9_init_indirectctx_bb()
1728 		*batch++ = 0;  in gen9_init_indirectctx_bb()
1729 		*batch++ = 0;  in gen9_init_indirectctx_bb()
1730 		*batch++ = 0;  in gen9_init_indirectctx_bb()
1733 	*batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;  in gen9_init_indirectctx_bb()
1736 	while ((unsigned long)batch % CACHELINE_BYTES)  in gen9_init_indirectctx_bb()
1737 		*batch++ = MI_NOOP;  in gen9_init_indirectctx_bb()
1739 	return batch;  in gen9_init_indirectctx_bb()
1773 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1783 	void *batch, *batch_ptr;  in lrc_init_wa_ctx()  local
1823 	batch = i915_gem_object_pin_map(wa_ctx->vma->obj, I915_MAP_WB);  in lrc_init_wa_ctx()
1824 	if (IS_ERR(batch)) {  in lrc_init_wa_ctx()
1825 		err = PTR_ERR(batch);  in lrc_init_wa_ctx()
1834 	batch_ptr = batch;  in lrc_init_wa_ctx()
1836 		wa_bb[i]->offset = batch_ptr - batch;  in lrc_init_wa_ctx()
1844 		wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);  in lrc_init_wa_ctx()
1846 	GEM_BUG_ON(batch_ptr - batch > CTX_WA_BB_SIZE);  in lrc_init_wa_ctx()
1848 	__i915_gem_object_flush_map(wa_ctx->vma->obj, 0, batch_ptr - batch);  in lrc_init_wa_ctx()