19 	u32 cmd, *cs;  in gen2_emit_flush()  local
25 	cs = intel_ring_begin(rq, 2 + 4 * num_store_dw);  in gen2_emit_flush()
26 	if (IS_ERR(cs))  in gen2_emit_flush()
27 		return PTR_ERR(cs);  in gen2_emit_flush()
29 	*cs++ = cmd;  in gen2_emit_flush()
31 		*cs++ = MI_STORE_DWORD_INDEX;  in gen2_emit_flush()
32 		*cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);  in gen2_emit_flush()
33 		*cs++ = 0;  in gen2_emit_flush()
34 		*cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;  in gen2_emit_flush()
36 	*cs++ = cmd;  in gen2_emit_flush()
38 	intel_ring_advance(rq, cs);  in gen2_emit_flush()
45 	u32 cmd, *cs;  in gen4_emit_flush_rcs()  local
87 	cs = intel_ring_begin(rq, i);  in gen4_emit_flush_rcs()
88 	if (IS_ERR(cs))  in gen4_emit_flush_rcs()
89 		return PTR_ERR(cs);  in gen4_emit_flush_rcs()
91 	*cs++ = cmd;  in gen4_emit_flush_rcs()
104 		*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;  in gen4_emit_flush_rcs()
105 		*cs++ = intel_gt_scratch_offset(rq->engine->gt,  in gen4_emit_flush_rcs()
108 		*cs++ = 0;  in gen4_emit_flush_rcs()
109 		*cs++ = 0;  in gen4_emit_flush_rcs()
112 			*cs++ = MI_FLUSH;  in gen4_emit_flush_rcs()
114 		*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;  in gen4_emit_flush_rcs()
115 		*cs++ = intel_gt_scratch_offset(rq->engine->gt,  in gen4_emit_flush_rcs()
118 		*cs++ = 0;  in gen4_emit_flush_rcs()
119 		*cs++ = 0;  in gen4_emit_flush_rcs()
122 	*cs++ = cmd;  in gen4_emit_flush_rcs()
124 	intel_ring_advance(rq, cs);  in gen4_emit_flush_rcs()
131 	u32 *cs;  in gen4_emit_flush_vcs()  local
133 	cs = intel_ring_begin(rq, 2);  in gen4_emit_flush_vcs()
134 	if (IS_ERR(cs))  in gen4_emit_flush_vcs()
135 		return PTR_ERR(cs);  in gen4_emit_flush_vcs()
137 	*cs++ = MI_FLUSH;  in gen4_emit_flush_vcs()
138 	*cs++ = MI_NOOP;  in gen4_emit_flush_vcs()
139 	intel_ring_advance(rq, cs);  in gen4_emit_flush_vcs()
144 static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,  in __gen2_emit_breadcrumb()  argument
150 	*cs++ = MI_FLUSH;  in __gen2_emit_breadcrumb()
153 		*cs++ = MI_STORE_DWORD_INDEX;  in __gen2_emit_breadcrumb()
154 		*cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32);  in __gen2_emit_breadcrumb()
155 		*cs++ = rq->fence.seqno;  in __gen2_emit_breadcrumb()
159 		*cs++ = MI_STORE_DWORD_INDEX;  in __gen2_emit_breadcrumb()
160 		*cs++ = I915_GEM_HWS_SEQNO_ADDR;  in __gen2_emit_breadcrumb()
161 		*cs++ = rq->fence.seqno;  in __gen2_emit_breadcrumb()
164 	*cs++ = MI_USER_INTERRUPT;  in __gen2_emit_breadcrumb()
166 	rq->tail = intel_ring_offset(rq, cs);  in __gen2_emit_breadcrumb()
169 	return cs;  in __gen2_emit_breadcrumb()
172 u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)  in gen3_emit_breadcrumb()  argument
174 	return __gen2_emit_breadcrumb(rq, cs, 16, 8);  in gen3_emit_breadcrumb()
177 u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)  in gen5_emit_breadcrumb()  argument
179 	return __gen2_emit_breadcrumb(rq, cs, 8, 8);  in gen5_emit_breadcrumb()
190 	u32 *cs, cs_offset =  in i830_emit_bb_start()  local
196 	cs = intel_ring_begin(rq, 6);  in i830_emit_bb_start()
197 	if (IS_ERR(cs))  in i830_emit_bb_start()
198 		return PTR_ERR(cs);  in i830_emit_bb_start()
201 	*cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;  in i830_emit_bb_start()
202 	*cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096;  in i830_emit_bb_start()
203 	*cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */  in i830_emit_bb_start()
204 	*cs++ = cs_offset;  in i830_emit_bb_start()
205 	*cs++ = 0xdeadbeef;  in i830_emit_bb_start()
206 	*cs++ = MI_NOOP;  in i830_emit_bb_start()
207 	intel_ring_advance(rq, cs);  in i830_emit_bb_start()
213 		cs = intel_ring_begin(rq, 6 + 2);  in i830_emit_bb_start()
214 		if (IS_ERR(cs))  in i830_emit_bb_start()
215 			return PTR_ERR(cs);  in i830_emit_bb_start()
222 		*cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);  in i830_emit_bb_start()
223 		*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096;  in i830_emit_bb_start()
224 		*cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;  in i830_emit_bb_start()
225 		*cs++ = cs_offset;  in i830_emit_bb_start()
226 		*cs++ = 4096;  in i830_emit_bb_start()
227 		*cs++ = offset;  in i830_emit_bb_start()
229 		*cs++ = MI_FLUSH;  in i830_emit_bb_start()
230 		*cs++ = MI_NOOP;  in i830_emit_bb_start()
231 		intel_ring_advance(rq, cs);  in i830_emit_bb_start()
240 	cs = intel_ring_begin(rq, 2);  in i830_emit_bb_start()
241 	if (IS_ERR(cs))  in i830_emit_bb_start()
242 		return PTR_ERR(cs);  in i830_emit_bb_start()
244 	*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;  in i830_emit_bb_start()
245 	*cs++ = offset;  in i830_emit_bb_start()
246 	intel_ring_advance(rq, cs);  in i830_emit_bb_start()
255 	u32 *cs;  in gen3_emit_bb_start()  local
260 	cs = intel_ring_begin(rq, 2);  in gen3_emit_bb_start()
261 	if (IS_ERR(cs))  in gen3_emit_bb_start()
262 		return PTR_ERR(cs);  in gen3_emit_bb_start()
264 	*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;  in gen3_emit_bb_start()
265 	*cs++ = offset;  in gen3_emit_bb_start()
266 	intel_ring_advance(rq, cs);  in gen3_emit_bb_start()
276 	u32 *cs;  in gen4_emit_bb_start()  local
282 	cs = intel_ring_begin(rq, 2);  in gen4_emit_bb_start()
283 	if (IS_ERR(cs))  in gen4_emit_bb_start()
284 		return PTR_ERR(cs);  in gen4_emit_bb_start()
286 	*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | security;  in gen4_emit_bb_start()
287 	*cs++ = offset;  in gen4_emit_bb_start()
288 	intel_ring_advance(rq, cs);  in gen4_emit_bb_start()