403 		if (wm->wm[0].enable && !wm->sagv.wm0.enable)  in tgl_crtc_can_enable_sagv()
1390 		return &wm->sagv.wm0;  in skl_plane_wm_level()
1650 		skl_check_wm_level(&wm->sagv.wm0, ddb);  in skl_crtc_allocate_plane_ddb()
2010 	struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0;  in tgl_compute_sagv_wm()
2025 				      const struct skl_wm_level *wm0,  in skl_compute_transition_wm()  argument
2065 	wm0_blocks = wm0->blocks - 1;  in skl_compute_transition_wm()
2082 	trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, blocks + 1);  in skl_compute_transition_wm()
2110 					  &wm->sagv.wm0, &wm_params);  in skl_build_plane_wm_single()
2311 			wm->sagv.wm0.enable = false;  in skl_wm_check_vblank()
2403 				   &wm->sagv.wm0);  in skl_write_plane_wm()
2438 				   &wm->sagv.wm0);  in skl_write_cursor_wm()
2472 		skl_wm_level_equals(&wm1->sagv.wm0, &wm2->sagv.wm0) &&  in skl_plane_wm_equals()
2728 				    enast(old_wm->sagv.wm0.enable),  in skl_print_wm_changes()
2735 				    enast(new_wm->sagv.wm0.enable),  in skl_print_wm_changes()
2751 				    enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines,  in skl_print_wm_changes()
2762 				    enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines,  in skl_print_wm_changes()
2774 				    old_wm->sagv.wm0.blocks,  in skl_print_wm_changes()
2781 				    new_wm->sagv.wm0.blocks,  in skl_print_wm_changes()
2793 				    old_wm->sagv.wm0.min_ddb_alloc,  in skl_print_wm_changes()
2800 				    new_wm->sagv.wm0.min_ddb_alloc,  in skl_print_wm_changes()
2828 		if (!skl_wm_level_equals(&old_wm->sagv.wm0, &new_wm->sagv.wm0) ||  in skl_plane_selected_wm_equals()
2978 			skl_wm_level_from_reg_val(val, &wm->sagv.wm0);  in skl_pipe_wm_get_hw_state()
2987 			wm->sagv.wm0 = wm->wm[0];  in skl_pipe_wm_get_hw_state()
3207 		hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;  in intel_wm_state_verify()
3208 		sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;  in intel_wm_state_verify()