Lines Matching refs:t11_t12
1296 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; in intel_pps_readout_hw_state()
1298 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; in intel_pps_readout_hw_state()
1310 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); in intel_pps_dump_state()
1323 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { in intel_pps_verify_state()
1333 delays->t10 || delays->t11_t12; in pps_delays_valid()
1368 vbt->t11_t12 = max_t(u16, vbt->t11_t12, 1300 * 10); in pps_init_delays_vbt()
1371 vbt->t11_t12); in pps_init_delays_vbt()
1378 vbt->t11_t12 += 100 * 10; in pps_init_delays_vbt()
1400 spec->t11_t12 = (510 + 100) * 10; in pps_init_delays_spec()
1430 assign_final(t11_t12); in pps_init_delays()
1438 intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12); in pps_init_delays()
1465 final->t11_t12 = roundup(final->t11_t12, 100 * 10); in pps_init_delays()
1544 … * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); in pps_init_registers()
1548 DIV_ROUND_UP(seq->t11_t12, 1000))); in pps_init_registers()