Lines Matching refs:hw_state
84 struct intel_dpll_hw_state *hw_state);
111 const struct intel_dpll_hw_state *hw_state);
166 struct intel_dpll_hw_state hw_state; in assert_shared_dpll() local
172 cur_state = intel_dpll_get_hw_state(dev_priv, pll, &hw_state); in assert_shared_dpll()
333 &shared_dpll[i].hw_state, in intel_find_shared_dpll()
391 shared_dpll[id].hw_state = *pll_state; in intel_reference_shared_dpll()
477 struct intel_dpll_hw_state *hw_state) in ibx_pch_dpll_get_hw_state() argument
489 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
490 hw_state->fp0 = intel_de_read(dev_priv, PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
491 hw_state->fp1 = intel_de_read(dev_priv, PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
518 intel_de_write(dev_priv, PCH_FP0(id), pll->state.hw_state.fp0); in ibx_pch_dpll_enable()
519 intel_de_write(dev_priv, PCH_FP1(id), pll->state.hw_state.fp1); in ibx_pch_dpll_enable()
521 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
532 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
593 const struct intel_dpll_hw_state *hw_state) in ibx_dump_hw_state() argument
598 hw_state->dpll, in ibx_dump_hw_state()
599 hw_state->dpll_md, in ibx_dump_hw_state()
600 hw_state->fp0, in ibx_dump_hw_state()
601 hw_state->fp1); in ibx_dump_hw_state()
629 intel_de_write(dev_priv, WRPLL_CTL(id), pll->state.hw_state.wrpll); in hsw_ddi_wrpll_enable()
637 intel_de_write(dev_priv, SPLL_CTL, pll->state.hw_state.spll); in hsw_ddi_spll_enable()
676 struct intel_dpll_hw_state *hw_state) in hsw_ddi_wrpll_get_hw_state() argument
688 hw_state->wrpll = val; in hsw_ddi_wrpll_get_hw_state()
697 struct intel_dpll_hw_state *hw_state) in hsw_ddi_spll_get_hw_state() argument
708 hw_state->spll = val; in hsw_ddi_spll_get_hw_state()
1174 const struct intel_dpll_hw_state *hw_state) in hsw_dump_hw_state() argument
1177 hw_state->wrpll, hw_state->spll); in hsw_dump_hw_state()
1206 struct intel_dpll_hw_state *hw_state) in hsw_ddi_lcpll_get_hw_state() argument
1275 pll->state.hw_state.ctrl1 << (id * 6)); in skl_ddi_pll_write_ctrl1()
1287 intel_de_write(dev_priv, regs[id].cfgcr1, pll->state.hw_state.cfgcr1); in skl_ddi_pll_enable()
1288 intel_de_write(dev_priv, regs[id].cfgcr2, pll->state.hw_state.cfgcr2); in skl_ddi_pll_enable()
1323 struct intel_dpll_hw_state *hw_state) in skl_ddi_pll_get_hw_state() argument
1343 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_pll_get_hw_state()
1347 hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
1348 hw_state->cfgcr2 = intel_de_read(dev_priv, regs[id].cfgcr2); in skl_ddi_pll_get_hw_state()
1360 struct intel_dpll_hw_state *hw_state) in skl_ddi_dpll0_get_hw_state() argument
1381 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_dpll0_get_hw_state()
1877 const struct intel_dpll_hw_state *hw_state) in skl_dump_hw_state() argument
1881 hw_state->ctrl1, in skl_dump_hw_state()
1882 hw_state->cfgcr1, in skl_dump_hw_state()
1883 hw_state->cfgcr2); in skl_dump_hw_state()
1946 PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, pll->state.hw_state.ebb0); in bxt_ddi_pll_enable()
1950 PORT_PLL_M2_INT_MASK, pll->state.hw_state.pll0); in bxt_ddi_pll_enable()
1954 PORT_PLL_N_MASK, pll->state.hw_state.pll1); in bxt_ddi_pll_enable()
1958 PORT_PLL_M2_FRAC_MASK, pll->state.hw_state.pll2); in bxt_ddi_pll_enable()
1962 PORT_PLL_M2_FRAC_ENABLE, pll->state.hw_state.pll3); in bxt_ddi_pll_enable()
1969 temp |= pll->state.hw_state.pll6; in bxt_ddi_pll_enable()
1974 PORT_PLL_TARGET_CNT_MASK, pll->state.hw_state.pll8); in bxt_ddi_pll_enable()
1977 PORT_PLL_LOCK_THRESHOLD_MASK, pll->state.hw_state.pll9); in bxt_ddi_pll_enable()
1982 temp |= pll->state.hw_state.pll10; in bxt_ddi_pll_enable()
1990 temp |= pll->state.hw_state.ebb4; in bxt_ddi_pll_enable()
2014 temp |= pll->state.hw_state.pcsdw12; in bxt_ddi_pll_enable()
2039 struct intel_dpll_hw_state *hw_state) in bxt_ddi_pll_get_hw_state() argument
2061 hw_state->ebb0 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch)); in bxt_ddi_pll_get_hw_state()
2062 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; in bxt_ddi_pll_get_hw_state()
2064 hw_state->ebb4 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)); in bxt_ddi_pll_get_hw_state()
2065 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; in bxt_ddi_pll_get_hw_state()
2067 hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_get_hw_state()
2068 hw_state->pll0 &= PORT_PLL_M2_INT_MASK; in bxt_ddi_pll_get_hw_state()
2070 hw_state->pll1 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1)); in bxt_ddi_pll_get_hw_state()
2071 hw_state->pll1 &= PORT_PLL_N_MASK; in bxt_ddi_pll_get_hw_state()
2073 hw_state->pll2 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2)); in bxt_ddi_pll_get_hw_state()
2074 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; in bxt_ddi_pll_get_hw_state()
2076 hw_state->pll3 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3)); in bxt_ddi_pll_get_hw_state()
2077 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_pll_get_hw_state()
2079 hw_state->pll6 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6)); in bxt_ddi_pll_get_hw_state()
2080 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | in bxt_ddi_pll_get_hw_state()
2084 hw_state->pll8 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8)); in bxt_ddi_pll_get_hw_state()
2085 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; in bxt_ddi_pll_get_hw_state()
2087 hw_state->pll9 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9)); in bxt_ddi_pll_get_hw_state()
2088 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; in bxt_ddi_pll_get_hw_state()
2090 hw_state->pll10 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10)); in bxt_ddi_pll_get_hw_state()
2091 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | in bxt_ddi_pll_get_hw_state()
2099 hw_state->pcsdw12 = intel_de_read(dev_priv, in bxt_ddi_pll_get_hw_state()
2101 if (intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) in bxt_ddi_pll_get_hw_state()
2104 hw_state->pcsdw12, in bxt_ddi_pll_get_hw_state()
2107 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; in bxt_ddi_pll_get_hw_state()
2330 const struct intel_dpll_hw_state *hw_state) in bxt_dump_hw_state() argument
2335 hw_state->ebb0, in bxt_dump_hw_state()
2336 hw_state->ebb4, in bxt_dump_hw_state()
2337 hw_state->pll0, in bxt_dump_hw_state()
2338 hw_state->pll1, in bxt_dump_hw_state()
2339 hw_state->pll2, in bxt_dump_hw_state()
2340 hw_state->pll3, in bxt_dump_hw_state()
2341 hw_state->pll6, in bxt_dump_hw_state()
2342 hw_state->pll8, in bxt_dump_hw_state()
2343 hw_state->pll9, in bxt_dump_hw_state()
2344 hw_state->pll10, in bxt_dump_hw_state()
2345 hw_state->pcsdw12); in bxt_dump_hw_state()
3143 crtc_state->dpll_hw_state = port_dpll->hw_state; in icl_set_active_port_dpll()
3187 icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); in icl_compute_combo_phy_dpll()
3193 &port_dpll->hw_state); in icl_compute_combo_phy_dpll()
3245 &port_dpll->hw_state, in icl_get_combo_phy_dpll()
3251 port_dpll->pll, &port_dpll->hw_state); in icl_get_combo_phy_dpll()
3274 icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3277 ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3285 &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3304 &port_dpll->hw_state, in icl_get_tc_phy_dplls()
3309 port_dpll->pll, &port_dpll->hw_state); in icl_get_tc_phy_dplls()
3316 &port_dpll->hw_state, in icl_get_tc_phy_dplls()
3323 port_dpll->pll, &port_dpll->hw_state); in icl_get_tc_phy_dplls()
3398 struct intel_dpll_hw_state *hw_state) in mg_pll_get_hw_state() argument
3417 hw_state->mg_refclkin_ctl = intel_de_read(dev_priv, in mg_pll_get_hw_state()
3419 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; in mg_pll_get_hw_state()
3421 hw_state->mg_clktop2_coreclkctl1 = in mg_pll_get_hw_state()
3423 hw_state->mg_clktop2_coreclkctl1 &= in mg_pll_get_hw_state()
3426 hw_state->mg_clktop2_hsclkctl = in mg_pll_get_hw_state()
3428 hw_state->mg_clktop2_hsclkctl &= in mg_pll_get_hw_state()
3434 hw_state->mg_pll_div0 = intel_de_read(dev_priv, MG_PLL_DIV0(tc_port)); in mg_pll_get_hw_state()
3435 hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port)); in mg_pll_get_hw_state()
3436 hw_state->mg_pll_lf = intel_de_read(dev_priv, MG_PLL_LF(tc_port)); in mg_pll_get_hw_state()
3437 hw_state->mg_pll_frac_lock = intel_de_read(dev_priv, in mg_pll_get_hw_state()
3439 hw_state->mg_pll_ssc = intel_de_read(dev_priv, MG_PLL_SSC(tc_port)); in mg_pll_get_hw_state()
3441 hw_state->mg_pll_bias = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port)); in mg_pll_get_hw_state()
3442 hw_state->mg_pll_tdc_coldst_bias = in mg_pll_get_hw_state()
3446 hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART; in mg_pll_get_hw_state()
3447 hw_state->mg_pll_bias_mask = 0; in mg_pll_get_hw_state()
3449 hw_state->mg_pll_tdc_coldst_bias_mask = -1U; in mg_pll_get_hw_state()
3450 hw_state->mg_pll_bias_mask = -1U; in mg_pll_get_hw_state()
3453 hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask; in mg_pll_get_hw_state()
3454 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask; in mg_pll_get_hw_state()
3464 struct intel_dpll_hw_state *hw_state) in dkl_pll_get_hw_state() argument
3485 hw_state->mg_refclkin_ctl = intel_dkl_phy_read(dev_priv, in dkl_pll_get_hw_state()
3487 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; in dkl_pll_get_hw_state()
3489 hw_state->mg_clktop2_hsclkctl = in dkl_pll_get_hw_state()
3491 hw_state->mg_clktop2_hsclkctl &= in dkl_pll_get_hw_state()
3497 hw_state->mg_clktop2_coreclkctl1 = in dkl_pll_get_hw_state()
3499 hw_state->mg_clktop2_coreclkctl1 &= in dkl_pll_get_hw_state()
3502 hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port)); in dkl_pll_get_hw_state()
3506 hw_state->mg_pll_div0 &= val; in dkl_pll_get_hw_state()
3508 hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port)); in dkl_pll_get_hw_state()
3509 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | in dkl_pll_get_hw_state()
3512 hw_state->mg_pll_ssc = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port)); in dkl_pll_get_hw_state()
3513 hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | in dkl_pll_get_hw_state()
3518 hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port)); in dkl_pll_get_hw_state()
3519 hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | in dkl_pll_get_hw_state()
3522 hw_state->mg_pll_tdc_coldst_bias = in dkl_pll_get_hw_state()
3524 hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK | in dkl_pll_get_hw_state()
3535 struct intel_dpll_hw_state *hw_state, in icl_pll_get_hw_state() argument
3553 hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3554 hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3556 hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3557 hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3559 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3561 hw_state->cfgcr1 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3564 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3566 hw_state->cfgcr1 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3569 hw_state->div0 = intel_de_read(dev_priv, TGL_DPLL0_DIV0(id)); in icl_pll_get_hw_state()
3570 hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK; in icl_pll_get_hw_state()
3575 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3577 hw_state->cfgcr1 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3580 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3582 hw_state->cfgcr1 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3595 struct intel_dpll_hw_state *hw_state) in combo_pll_get_hw_state() argument
3599 return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg); in combo_pll_get_hw_state()
3604 struct intel_dpll_hw_state *hw_state) in tbt_pll_get_hw_state() argument
3606 return icl_pll_get_hw_state(dev_priv, pll, hw_state, TBT_PLL_ENABLE); in tbt_pll_get_hw_state()
3612 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; in icl_dpll_write() local
3640 intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0); in icl_dpll_write()
3641 intel_de_write(dev_priv, cfgcr1_reg, hw_state->cfgcr1); in icl_dpll_write()
3647 TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0); in icl_dpll_write()
3654 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; in icl_mg_pll_write() local
3664 MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl); in icl_mg_pll_write()
3668 hw_state->mg_clktop2_coreclkctl1); in icl_mg_pll_write()
3675 hw_state->mg_clktop2_hsclkctl); in icl_mg_pll_write()
3677 intel_de_write(dev_priv, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); in icl_mg_pll_write()
3678 intel_de_write(dev_priv, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); in icl_mg_pll_write()
3679 intel_de_write(dev_priv, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); in icl_mg_pll_write()
3681 hw_state->mg_pll_frac_lock); in icl_mg_pll_write()
3682 intel_de_write(dev_priv, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); in icl_mg_pll_write()
3685 hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias); in icl_mg_pll_write()
3688 hw_state->mg_pll_tdc_coldst_bias_mask, in icl_mg_pll_write()
3689 hw_state->mg_pll_tdc_coldst_bias); in icl_mg_pll_write()
3697 struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; in dkl_pll_write() local
3708 val |= hw_state->mg_refclkin_ctl; in dkl_pll_write()
3713 val |= hw_state->mg_clktop2_coreclkctl1; in dkl_pll_write()
3721 val |= hw_state->mg_clktop2_hsclkctl; in dkl_pll_write()
3728 hw_state->mg_pll_div0); in dkl_pll_write()
3733 val |= hw_state->mg_pll_div1; in dkl_pll_write()
3741 val |= hw_state->mg_pll_ssc; in dkl_pll_write()
3747 val |= hw_state->mg_pll_bias; in dkl_pll_write()
3753 val |= hw_state->mg_pll_tdc_coldst_bias; in dkl_pll_write()
3949 const struct intel_dpll_hw_state *hw_state) in icl_dump_hw_state() argument
3958 hw_state->cfgcr0, hw_state->cfgcr1, in icl_dump_hw_state()
3959 hw_state->div0, in icl_dump_hw_state()
3960 hw_state->mg_refclkin_ctl, in icl_dump_hw_state()
3961 hw_state->mg_clktop2_coreclkctl1, in icl_dump_hw_state()
3962 hw_state->mg_clktop2_hsclkctl, in icl_dump_hw_state()
3963 hw_state->mg_pll_div0, in icl_dump_hw_state()
3964 hw_state->mg_pll_div1, in icl_dump_hw_state()
3965 hw_state->mg_pll_lf, in icl_dump_hw_state()
3966 hw_state->mg_pll_frac_lock, in icl_dump_hw_state()
3967 hw_state->mg_pll_ssc, in icl_dump_hw_state()
3968 hw_state->mg_pll_bias, in icl_dump_hw_state()
3969 hw_state->mg_pll_tdc_coldst_bias); in icl_dump_hw_state()
4331 struct intel_dpll_hw_state *hw_state) in intel_dpll_get_hw_state() argument
4333 return pll->info->funcs->get_hw_state(i915, pll, hw_state); in intel_dpll_get_hw_state()
4341 pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state); in readout_dpll_hw_state()
4414 const struct intel_dpll_hw_state *hw_state) in intel_dpll_dump_hw_state() argument
4417 dev_priv->display.dpll.mgr->dump_hw_state(dev_priv, hw_state); in intel_dpll_dump_hw_state()
4425 hw_state->dpll, in intel_dpll_dump_hw_state()
4426 hw_state->dpll_md, in intel_dpll_dump_hw_state()
4427 hw_state->fp0, in intel_dpll_dump_hw_state()
4428 hw_state->fp1); in intel_dpll_dump_hw_state()
4483 pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state, in verify_single_dpll_state()