1238 	i915_reg_t ctl, cfgcr1, cfgcr2;  member
1251 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
1257 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
1263 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
1287 	intel_de_write(dev_priv, regs[id].cfgcr1, pll->state.hw_state.cfgcr1);  in skl_ddi_pll_enable()
1289 	intel_de_posting_read(dev_priv, regs[id].cfgcr1);  in skl_ddi_pll_enable()
1347 		hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1);  in skl_ddi_pll_get_hw_state()
1689 	dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *  in skl_ddi_wrpll_get_freq()
1692 	dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *  in skl_ddi_wrpll_get_freq()
1705 	u32 ctrl1, cfgcr1, cfgcr2;  in skl_ddi_hdmi_pll_dividers()  local
1721 	cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |  in skl_ddi_hdmi_pll_dividers()
1732 	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;  in skl_ddi_hdmi_pll_dividers()
1882 		      hw_state->cfgcr1,  in skl_dump_hw_state()
2694 	p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;  in icl_ddi_combo_pll_get_freq()
2695 	p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;  in icl_ddi_combo_pll_get_freq()
2697 	if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))  in icl_ddi_combo_pll_get_freq()
2698 		p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>  in icl_ddi_combo_pll_get_freq()
2759 	pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |  in icl_calc_dpll_state()
2765 		pll_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;  in icl_calc_dpll_state()
2767 		pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;  in icl_calc_dpll_state()
3554 		hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id));  in icl_pll_get_hw_state()
3557 		hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));  in icl_pll_get_hw_state()
3561 		hw_state->cfgcr1 = intel_de_read(dev_priv,  in icl_pll_get_hw_state()
3566 		hw_state->cfgcr1 = intel_de_read(dev_priv,  in icl_pll_get_hw_state()
3577 			hw_state->cfgcr1 = intel_de_read(dev_priv,  in icl_pll_get_hw_state()
3582 			hw_state->cfgcr1 = intel_de_read(dev_priv,  in icl_pll_get_hw_state()
3641 	intel_de_write(dev_priv, cfgcr1_reg, hw_state->cfgcr1);  in icl_dpll_write()
3958 		    hw_state->cfgcr0, hw_state->cfgcr1,  in icl_dump_hw_state()