1113 	int n_entries, ln;  in icl_ddi_combo_vswing_program()  local
1139 	for (ln = 0; ln < 4; ln++) {  in icl_ddi_combo_vswing_program()
1140 		int level = intel_ddi_level(encoder, crtc_state, ln);  in icl_ddi_combo_vswing_program()
1142 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),  in icl_ddi_combo_vswing_program()
1151 	for (ln = 0; ln < 4; ln++) {  in icl_ddi_combo_vswing_program()
1152 		int level = intel_ddi_level(encoder, crtc_state, ln);  in icl_ddi_combo_vswing_program()
1154 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),  in icl_ddi_combo_vswing_program()
1162 	for (ln = 0; ln < 4; ln++) {  in icl_ddi_combo_vswing_program()
1163 		int level = intel_ddi_level(encoder, crtc_state, ln);  in icl_ddi_combo_vswing_program()
1165 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),  in icl_ddi_combo_vswing_program()
1177 	int ln;  in icl_combo_phy_set_signal_levels()  local
1198 	for (ln = 0; ln < 4; ln++) {  in icl_combo_phy_set_signal_levels()
1199 		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),  in icl_combo_phy_set_signal_levels()
1201 			     icl_combo_phy_loadgen_select(crtc_state, ln));  in icl_combo_phy_set_signal_levels()
1228 	int n_entries, ln;  in icl_mg_phy_set_signal_levels()  local
1237 	for (ln = 0; ln < 2; ln++) {  in icl_mg_phy_set_signal_levels()
1238 		intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1240 		intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1245 	for (ln = 0; ln < 2; ln++) {  in icl_mg_phy_set_signal_levels()
1248 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);  in icl_mg_phy_set_signal_levels()
1250 		intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1254 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);  in icl_mg_phy_set_signal_levels()
1256 		intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1262 	for (ln = 0; ln < 2; ln++) {  in icl_mg_phy_set_signal_levels()
1265 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);  in icl_mg_phy_set_signal_levels()
1267 		intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1274 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);  in icl_mg_phy_set_signal_levels()
1276 		intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1291 	for (ln = 0; ln < 2; ln++) {  in icl_mg_phy_set_signal_levels()
1292 		intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1298 	for (ln = 0; ln < 2; ln++) {  in icl_mg_phy_set_signal_levels()
1299 		intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1306 		intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1315 	for (ln = 0; ln < 2; ln++) {  in icl_mg_phy_set_signal_levels()
1316 		intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1318 		intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),  in icl_mg_phy_set_signal_levels()
1329 	int n_entries, ln;  in tgl_dkl_phy_set_signal_levels()  local
1338 	for (ln = 0; ln < 2; ln++) {  in tgl_dkl_phy_set_signal_levels()
1341 		intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);  in tgl_dkl_phy_set_signal_levels()
1343 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);  in tgl_dkl_phy_set_signal_levels()
1345 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),  in tgl_dkl_phy_set_signal_levels()
1353 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);  in tgl_dkl_phy_set_signal_levels()
1355 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),  in tgl_dkl_phy_set_signal_levels()
1363 		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),  in tgl_dkl_phy_set_signal_levels()
1370 				if (ln == 0) {  in tgl_dkl_phy_set_signal_levels()
1382 			intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),  in tgl_dkl_phy_set_signal_levels()
3406 	int ln;  in adlp_tbt_to_dp_alt_switch_wa()  local
3408 	for (ln = 0; ln < 2; ln++)  in adlp_tbt_to_dp_alt_switch_wa()
3409 		intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);  in adlp_tbt_to_dp_alt_switch_wa()