199 	const struct drm_display_mode *mode, struct drm_display_mode *adj)  in armada_drm_crtc_mode_fixup()  argument
209 	drm_mode_set_crtcinfo(adj, CRTC_INTERLACE_HALVE_V);  in armada_drm_crtc_mode_fixup()
215 	if (armada_drm_crtc_mode_valid(crtc, adj) != MODE_OK)  in armada_drm_crtc_mode_fixup()
219 	ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);  in armada_drm_crtc_mode_fixup()
331 	struct drm_display_mode *adj = &crtc->state->adjusted_mode;  in armada_drm_crtc_mode_set_nofb()  local
337 	bool interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);  in armada_drm_crtc_mode_set_nofb()
340 	rm = adj->crtc_hsync_start - adj->crtc_hdisplay;  in armada_drm_crtc_mode_set_nofb()
341 	lm = adj->crtc_htotal - adj->crtc_hsync_end;  in armada_drm_crtc_mode_set_nofb()
342 	bm = adj->crtc_vsync_start - adj->crtc_vdisplay;  in armada_drm_crtc_mode_set_nofb()
343 	tm = adj->crtc_vtotal - adj->crtc_vsync_end;  in armada_drm_crtc_mode_set_nofb()
346 		      crtc->base.id, crtc->name, DRM_MODE_ARG(adj));  in armada_drm_crtc_mode_set_nofb()
350 	dcrtc->variant->compute_clock(dcrtc, adj, &sclk);  in armada_drm_crtc_mode_set_nofb()
358 	dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |  in armada_drm_crtc_mode_set_nofb()
359 				    adj->crtc_htotal;  in armada_drm_crtc_mode_set_nofb()
361 	val = adj->crtc_hsync_start;  in armada_drm_crtc_mode_set_nofb()
366 		val -= adj->crtc_htotal / 2;  in armada_drm_crtc_mode_set_nofb()
375 	val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;  in armada_drm_crtc_mode_set_nofb()
388 	val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;  in armada_drm_crtc_mode_set_nofb()
400 	if (adj->flags & DRM_MODE_FLAG_NCSYNC)  in armada_drm_crtc_mode_set_nofb()
402 	if (adj->flags & DRM_MODE_FLAG_NHSYNC)  in armada_drm_crtc_mode_set_nofb()
404 	if (adj->flags & DRM_MODE_FLAG_NVSYNC)  in armada_drm_crtc_mode_set_nofb()