Lines Matching refs:pi
367 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi() local
369 return pi; in kv_get_pi()
449 struct kv_power_info *pi = kv_get_pi(adev); in kv_do_enable_didt() local
452 if (pi->caps_sq_ramping) { in kv_do_enable_didt()
461 if (pi->caps_db_ramping) { in kv_do_enable_didt()
470 if (pi->caps_td_ramping) { in kv_do_enable_didt()
479 if (pi->caps_tcp_ramping) { in kv_do_enable_didt()
491 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_didt() local
494 if (pi->caps_sq_ramping || in kv_enable_didt()
495 pi->caps_db_ramping || in kv_enable_didt()
496 pi->caps_td_ramping || in kv_enable_didt()
497 pi->caps_tcp_ramping) { in kv_enable_didt()
519 struct kv_power_info *pi = kv_get_pi(adev);
521 if (pi->caps_cac) {
551 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_smc_cac() local
554 if (pi->caps_cac) { in kv_enable_smc_cac()
558 pi->cac_enabled = false; in kv_enable_smc_cac()
560 pi->cac_enabled = true; in kv_enable_smc_cac()
561 } else if (pi->cac_enabled) { in kv_enable_smc_cac()
563 pi->cac_enabled = false; in kv_enable_smc_cac()
572 struct kv_power_info *pi = kv_get_pi(adev); in kv_process_firmware_header() local
578 &tmp, pi->sram_end); in kv_process_firmware_header()
581 pi->dpm_table_start = tmp; in kv_process_firmware_header()
585 &tmp, pi->sram_end); in kv_process_firmware_header()
588 pi->soft_regs_start = tmp; in kv_process_firmware_header()
595 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_dpm_voltage_scaling() local
598 pi->graphics_voltage_change_enable = 1; in kv_enable_dpm_voltage_scaling()
601 pi->dpm_table_start + in kv_enable_dpm_voltage_scaling()
603 &pi->graphics_voltage_change_enable, in kv_enable_dpm_voltage_scaling()
604 sizeof(u8), pi->sram_end); in kv_enable_dpm_voltage_scaling()
611 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_interval() local
614 pi->graphics_interval = 1; in kv_set_dpm_interval()
617 pi->dpm_table_start + in kv_set_dpm_interval()
619 &pi->graphics_interval, in kv_set_dpm_interval()
620 sizeof(u8), pi->sram_end); in kv_set_dpm_interval()
627 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_boot_state() local
631 pi->dpm_table_start + in kv_set_dpm_boot_state()
633 &pi->graphics_boot_level, in kv_set_dpm_boot_state()
634 sizeof(u8), pi->sram_end); in kv_set_dpm_boot_state()
652 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_divider_value() local
661 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
662 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
676 struct kv_power_info *pi = kv_get_pi(adev); in kv_convert_2bit_index_to_voltage() local
678 &pi->sys_info.vid_mapping_table, in kv_convert_2bit_index_to_voltage()
687 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_vid() local
689 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; in kv_set_vid()
690 pi->graphics_level[index].MinVddNb = in kv_set_vid()
698 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_at() local
700 pi->graphics_level[index].AT = cpu_to_be16((u16)at); in kv_set_at()
708 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enable() local
710 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; in kv_dpm_power_level_enable()
770 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_sclk_t() local
774 if (pi->caps_sclk_throttle_low_notification) { in kv_update_sclk_t()
775 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in kv_update_sclk_t()
778 pi->dpm_table_start + in kv_update_sclk_t()
781 sizeof(u32), pi->sram_end); in kv_update_sclk_t()
788 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_bootup_state() local
794 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
795 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
799 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
803 &pi->sys_info.sclk_voltage_mapping_table; in kv_program_bootup_state()
808 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
809 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
813 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
821 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_auto_thermal_throttling() local
824 pi->graphics_therm_throttle_enable = 1; in kv_enable_auto_thermal_throttling()
827 pi->dpm_table_start + in kv_enable_auto_thermal_throttling()
829 &pi->graphics_therm_throttle_enable, in kv_enable_auto_thermal_throttling()
830 sizeof(u8), pi->sram_end); in kv_enable_auto_thermal_throttling()
837 struct kv_power_info *pi = kv_get_pi(adev); in kv_upload_dpm_settings() local
841 pi->dpm_table_start + in kv_upload_dpm_settings()
843 (u8 *)&pi->graphics_level, in kv_upload_dpm_settings()
845 pi->sram_end); in kv_upload_dpm_settings()
851 pi->dpm_table_start + in kv_upload_dpm_settings()
853 &pi->graphics_dpm_level_count, in kv_upload_dpm_settings()
854 sizeof(u8), pi->sram_end); in kv_upload_dpm_settings()
866 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_clk_bypass() local
869 if (pi->caps_enable_dfs_bypass) { in kv_get_clk_bypass()
891 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_uvd_table() local
901 pi->uvd_level_count = 0; in kv_populate_uvd_table()
903 if (pi->high_voltage_t && in kv_populate_uvd_table()
904 (pi->high_voltage_t < table->entries[i].v)) in kv_populate_uvd_table()
907 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
908 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
909 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); in kv_populate_uvd_table()
911 pi->uvd_level[i].VClkBypassCntl = in kv_populate_uvd_table()
913 pi->uvd_level[i].DClkBypassCntl = in kv_populate_uvd_table()
920 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
926 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
928 pi->uvd_level_count++; in kv_populate_uvd_table()
932 pi->dpm_table_start + in kv_populate_uvd_table()
934 (u8 *)&pi->uvd_level_count, in kv_populate_uvd_table()
935 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
939 pi->uvd_interval = 1; in kv_populate_uvd_table()
942 pi->dpm_table_start + in kv_populate_uvd_table()
944 &pi->uvd_interval, in kv_populate_uvd_table()
945 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
950 pi->dpm_table_start + in kv_populate_uvd_table()
952 (u8 *)&pi->uvd_level, in kv_populate_uvd_table()
954 pi->sram_end); in kv_populate_uvd_table()
962 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_vce_table() local
972 pi->vce_level_count = 0; in kv_populate_vce_table()
974 if (pi->high_voltage_t && in kv_populate_vce_table()
975 pi->high_voltage_t < table->entries[i].v) in kv_populate_vce_table()
978 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
979 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_vce_table()
981 pi->vce_level[i].ClkBypassCntl = in kv_populate_vce_table()
988 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
990 pi->vce_level_count++; in kv_populate_vce_table()
994 pi->dpm_table_start + in kv_populate_vce_table()
996 (u8 *)&pi->vce_level_count, in kv_populate_vce_table()
998 pi->sram_end); in kv_populate_vce_table()
1002 pi->vce_interval = 1; in kv_populate_vce_table()
1005 pi->dpm_table_start + in kv_populate_vce_table()
1007 (u8 *)&pi->vce_interval, in kv_populate_vce_table()
1009 pi->sram_end); in kv_populate_vce_table()
1014 pi->dpm_table_start + in kv_populate_vce_table()
1016 (u8 *)&pi->vce_level, in kv_populate_vce_table()
1018 pi->sram_end); in kv_populate_vce_table()
1025 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_samu_table() local
1035 pi->samu_level_count = 0; in kv_populate_samu_table()
1037 if (pi->high_voltage_t && in kv_populate_samu_table()
1038 pi->high_voltage_t < table->entries[i].v) in kv_populate_samu_table()
1041 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_samu_table()
1042 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_samu_table()
1044 pi->samu_level[i].ClkBypassCntl = in kv_populate_samu_table()
1051 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
1053 pi->samu_level_count++; in kv_populate_samu_table()
1057 pi->dpm_table_start + in kv_populate_samu_table()
1059 (u8 *)&pi->samu_level_count, in kv_populate_samu_table()
1061 pi->sram_end); in kv_populate_samu_table()
1065 pi->samu_interval = 1; in kv_populate_samu_table()
1068 pi->dpm_table_start + in kv_populate_samu_table()
1070 (u8 *)&pi->samu_interval, in kv_populate_samu_table()
1072 pi->sram_end); in kv_populate_samu_table()
1077 pi->dpm_table_start + in kv_populate_samu_table()
1079 (u8 *)&pi->samu_level, in kv_populate_samu_table()
1081 pi->sram_end); in kv_populate_samu_table()
1091 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_acp_table() local
1101 pi->acp_level_count = 0; in kv_populate_acp_table()
1103 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_acp_table()
1104 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_acp_table()
1110 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
1112 pi->acp_level_count++; in kv_populate_acp_table()
1116 pi->dpm_table_start + in kv_populate_acp_table()
1118 (u8 *)&pi->acp_level_count, in kv_populate_acp_table()
1120 pi->sram_end); in kv_populate_acp_table()
1124 pi->acp_interval = 1; in kv_populate_acp_table()
1127 pi->dpm_table_start + in kv_populate_acp_table()
1129 (u8 *)&pi->acp_interval, in kv_populate_acp_table()
1131 pi->sram_end); in kv_populate_acp_table()
1136 pi->dpm_table_start + in kv_populate_acp_table()
1138 (u8 *)&pi->acp_level, in kv_populate_acp_table()
1140 pi->sram_end); in kv_populate_acp_table()
1149 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dfs_bypass_settings() local
1155 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1156 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1158 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1160 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1162 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1164 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1166 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1168 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1170 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1175 &pi->sys_info.sclk_voltage_mapping_table; in kv_calculate_dfs_bypass_settings()
1176 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1177 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1179 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1181 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1183 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1185 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1187 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1189 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1191 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1205 struct kv_power_info *pi = kv_get_pi(adev); in kv_reset_acp_boot_level() local
1207 pi->acp_boot_level = 0xff; in kv_reset_acp_boot_level()
1214 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_current_ps() local
1216 pi->current_rps = *rps; in kv_update_current_ps()
1217 pi->current_ps = *new_ps; in kv_update_current_ps()
1218 pi->current_rps.ps_priv = &pi->current_ps; in kv_update_current_ps()
1219 adev->pm.dpm.current_ps = &pi->current_rps; in kv_update_current_ps()
1226 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_requested_ps() local
1228 pi->requested_rps = *rps; in kv_update_requested_ps()
1229 pi->requested_ps = *new_ps; in kv_update_requested_ps()
1230 pi->requested_rps.ps_priv = &pi->requested_ps; in kv_update_requested_ps()
1231 adev->pm.dpm.requested_ps = &pi->requested_rps; in kv_update_requested_ps()
1237 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable_bapm() local
1240 if (pi->bapm_enable) { in kv_dpm_enable_bapm()
1262 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable() local
1308 if (pi->enable_auto_thermal_throttling) { in kv_dpm_enable()
1373 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_disable() local
1391 if (pi->caps_vce_pg) /* power on the VCE block */ in kv_dpm_disable()
1393 if (pi->caps_uvd_pg) /* power on the UVD block */ in kv_dpm_disable()
1410 struct kv_power_info *pi = kv_get_pi(adev);
1412 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1413 (u8 *)&value, sizeof(u16), pi->sram_end);
1419 struct kv_power_info *pi = kv_get_pi(adev);
1421 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1422 value, pi->sram_end);
1428 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_sclk_t() local
1430 pi->low_sclk_interrupt_t = 0; in kv_init_sclk_t()
1435 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_fps_limits() local
1438 if (pi->caps_fps) { in kv_init_fps_limits()
1442 pi->fps_high_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1444 pi->dpm_table_start + in kv_init_fps_limits()
1446 (u8 *)&pi->fps_high_t, in kv_init_fps_limits()
1447 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1450 pi->fps_low_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1453 pi->dpm_table_start + in kv_init_fps_limits()
1455 (u8 *)&pi->fps_low_t, in kv_init_fps_limits()
1456 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1464 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_powergate_state() local
1466 pi->uvd_power_gated = false; in kv_init_powergate_state()
1467 pi->vce_power_gated = false; in kv_init_powergate_state()
1468 pi->samu_power_gated = false; in kv_init_powergate_state()
1469 pi->acp_power_gated = false; in kv_init_powergate_state()
1499 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_uvd_dpm() local
1507 pi->uvd_boot_level = table->count - 1; in kv_update_uvd_dpm()
1509 pi->uvd_boot_level = 0; in kv_update_uvd_dpm()
1511 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { in kv_update_uvd_dpm()
1512 mask = 1 << pi->uvd_boot_level; in kv_update_uvd_dpm()
1518 pi->dpm_table_start + in kv_update_uvd_dpm()
1520 (uint8_t *)&pi->uvd_boot_level, in kv_update_uvd_dpm()
1521 sizeof(u8), pi->sram_end); in kv_update_uvd_dpm()
1551 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_vce_dpm() local
1557 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1558 pi->vce_boot_level = table->count - 1; in kv_update_vce_dpm()
1560 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); in kv_update_vce_dpm()
1563 pi->dpm_table_start + in kv_update_vce_dpm()
1565 (u8 *)&pi->vce_boot_level, in kv_update_vce_dpm()
1567 pi->sram_end); in kv_update_vce_dpm()
1571 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1574 (1 << pi->vce_boot_level)); in kv_update_vce_dpm()
1585 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_samu_dpm() local
1591 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1592 pi->samu_boot_level = table->count - 1; in kv_update_samu_dpm()
1594 pi->samu_boot_level = 0; in kv_update_samu_dpm()
1597 pi->dpm_table_start + in kv_update_samu_dpm()
1599 (u8 *)&pi->samu_boot_level, in kv_update_samu_dpm()
1601 pi->sram_end); in kv_update_samu_dpm()
1605 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1608 (1 << pi->samu_boot_level)); in kv_update_samu_dpm()
1621 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_boot_level() local
1624 if (!pi->caps_stable_p_state) { in kv_update_acp_boot_level()
1626 if (acp_boot_level != pi->acp_boot_level) { in kv_update_acp_boot_level()
1627 pi->acp_boot_level = acp_boot_level; in kv_update_acp_boot_level()
1630 (1 << pi->acp_boot_level)); in kv_update_acp_boot_level()
1637 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_dpm() local
1643 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1644 pi->acp_boot_level = table->count - 1; in kv_update_acp_dpm()
1646 pi->acp_boot_level = kv_get_acp_boot_level(adev); in kv_update_acp_dpm()
1649 pi->dpm_table_start + in kv_update_acp_dpm()
1651 (u8 *)&pi->acp_boot_level, in kv_update_acp_dpm()
1653 pi->sram_end); in kv_update_acp_dpm()
1657 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1660 (1 << pi->acp_boot_level)); in kv_update_acp_dpm()
1669 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_uvd() local
1671 pi->uvd_power_gated = gate; in kv_dpm_powergate_uvd()
1678 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1682 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1696 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_vce() local
1698 pi->vce_power_gated = gate; in kv_dpm_powergate_vce()
1705 if (pi->caps_vce_pg) /* power off the VCE block */ in kv_dpm_powergate_vce()
1708 if (pi->caps_vce_pg) /* power on the VCE block */ in kv_dpm_powergate_vce()
1720 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_samu() local
1722 if (pi->samu_power_gated == gate) in kv_dpm_powergate_samu()
1725 pi->samu_power_gated = gate; in kv_dpm_powergate_samu()
1729 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1732 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1740 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_acp() local
1742 if (pi->acp_power_gated == gate) in kv_dpm_powergate_acp()
1748 pi->acp_power_gated = gate; in kv_dpm_powergate_acp()
1752 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1755 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1765 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_valid_clock_range() local
1771 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1773 (i == (pi->graphics_dpm_level_count - 1))) { in kv_set_valid_clock_range()
1774 pi->lowest_valid = i; in kv_set_valid_clock_range()
1779 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1783 pi->highest_valid = i; in kv_set_valid_clock_range()
1785 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1786 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1787 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1788 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1790 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1794 &pi->sys_info.sclk_voltage_mapping_table; in kv_set_valid_clock_range()
1796 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1798 i == (int)(pi->graphics_dpm_level_count - 1)) { in kv_set_valid_clock_range()
1799 pi->lowest_valid = i; in kv_set_valid_clock_range()
1804 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1809 pi->highest_valid = i; in kv_set_valid_clock_range()
1811 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1813 table->entries[pi->highest_valid].sclk_frequency) > in kv_set_valid_clock_range()
1814 (table->entries[pi->lowest_valid].sclk_frequency - in kv_set_valid_clock_range()
1816 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1818 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1827 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_dfs_bypass_settings() local
1831 if (pi->caps_enable_dfs_bypass) { in kv_update_dfs_bypass_settings()
1833 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; in kv_update_dfs_bypass_settings()
1835 (pi->dpm_table_start + in kv_update_dfs_bypass_settings()
1837 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + in kv_update_dfs_bypass_settings()
1840 sizeof(u8), pi->sram_end); in kv_update_dfs_bypass_settings()
1849 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_nb_dpm() local
1853 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1856 pi->nb_dpm_enabled = true; in kv_enable_nb_dpm()
1859 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1862 pi->nb_dpm_enabled = false; in kv_enable_nb_dpm()
1897 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_pre_set_power_state() local
1904 &pi->requested_rps, in kv_dpm_pre_set_power_state()
1905 &pi->current_rps); in kv_dpm_pre_set_power_state()
1913 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_set_power_state() local
1914 struct amdgpu_ps *new_ps = &pi->requested_rps; in kv_dpm_set_power_state()
1915 struct amdgpu_ps *old_ps = &pi->current_rps; in kv_dpm_set_power_state()
1918 if (pi->bapm_enable) { in kv_dpm_set_power_state()
1927 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1956 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1988 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_post_set_power_state() local
1989 struct amdgpu_ps *new_ps = &pi->requested_rps; in kv_dpm_post_set_power_state()
2004 struct kv_power_info *pi = kv_get_pi(adev);
2019 kv_set_enabled_level(adev, pi->graphics_boot_level);
2027 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_max_power_limits_table() local
2029 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { in kv_construct_max_power_limits_table()
2030 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; in kv_construct_max_power_limits_table()
2032 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; in kv_construct_max_power_limits_table()
2035 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); in kv_construct_max_power_limits_table()
2038 table->mclk = pi->sys_info.nbp_memory_clock[0]; in kv_construct_max_power_limits_table()
2085 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_boot_state() local
2087 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in kv_construct_boot_state()
2088 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; in kv_construct_boot_state()
2089 pi->boot_pl.ds_divider_index = 0; in kv_construct_boot_state()
2090 pi->boot_pl.ss_divider_index = 0; in kv_construct_boot_state()
2091 pi->boot_pl.allow_gnb_slow = 1; in kv_construct_boot_state()
2092 pi->boot_pl.force_nbp_state = 0; in kv_construct_boot_state()
2093 pi->boot_pl.display_wm = 0; in kv_construct_boot_state()
2094 pi->boot_pl.vce_wm = 0; in kv_construct_boot_state()
2140 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_sleep_divider_id_from_clock() local
2148 if (!pi->caps_sclk_ds) in kv_get_sleep_divider_id_from_clock()
2162 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_high_voltage_limit() local
2169 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2171 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2178 &pi->sys_info.sclk_voltage_mapping_table; in kv_get_high_voltage_limit()
2181 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2183 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2199 struct kv_power_info *pi = kv_get_pi(adev); in kv_apply_state_adjust_rules() local
2221 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2251 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2252 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2260 &pi->sys_info.sclk_voltage_mapping_table; in kv_apply_state_adjust_rules()
2263 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2264 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2272 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2278 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2283 pi->battery_state = true; in kv_apply_state_adjust_rules()
2285 pi->battery_state = false; in kv_apply_state_adjust_rules()
2298 if (pi->sys_info.nb_dpm_enable) { in kv_apply_state_adjust_rules()
2299 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_apply_state_adjust_rules()
2300 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2301 pi->disable_nb_ps3_in_battery; in kv_apply_state_adjust_rules()
2313 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enabled_for_throttle() local
2315 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; in kv_dpm_power_level_enabled_for_throttle()
2320 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_ds_divider() local
2324 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_ds_divider()
2327 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_ds_divider()
2328 pi->graphics_level[i].DeepSleepDivId = in kv_calculate_ds_divider()
2330 be32_to_cpu(pi->graphics_level[i].SclkFrequency), in kv_calculate_ds_divider()
2338 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_nbps_level_settings() local
2345 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_nbps_level_settings()
2349 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2350 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2351 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2352 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2355 if (!pi->sys_info.nb_dpm_enable) in kv_calculate_nbps_level_settings()
2358 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_calculate_nbps_level_settings()
2359 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2362 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_nbps_level_settings()
2363 pi->graphics_level[i].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2365 if (pi->battery_state) in kv_calculate_nbps_level_settings()
2366 pi->graphics_level[0].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2368 pi->graphics_level[1].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2369 pi->graphics_level[2].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2370 pi->graphics_level[3].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2371 pi->graphics_level[4].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2374 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2375 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2376 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2377 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2380 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { in kv_calculate_nbps_level_settings()
2381 pi->graphics_level[pi->lowest_valid].UpH = 0x28; in kv_calculate_nbps_level_settings()
2382 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2383 if (pi->lowest_valid != pi->highest_valid) in kv_calculate_nbps_level_settings()
2384 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2392 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dpm_settings() local
2395 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_dpm_settings()
2398 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_dpm_settings()
2399 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; in kv_calculate_dpm_settings()
2406 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_graphics_levels() local
2414 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2416 if (pi->high_voltage_t && in kv_init_graphics_levels()
2417 (pi->high_voltage_t < in kv_init_graphics_levels()
2423 &pi->sys_info.vid_mapping_table, in kv_init_graphics_levels()
2426 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2428 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2432 &pi->sys_info.sclk_voltage_mapping_table; in kv_init_graphics_levels()
2434 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2436 if (pi->high_voltage_t && in kv_init_graphics_levels()
2437 pi->high_voltage_t < in kv_init_graphics_levels()
2443 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2445 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2455 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_new_levels() local
2459 if (i >= pi->lowest_valid && i <= pi->highest_valid) in kv_enable_new_levels()
2475 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_enabled_levels() local
2478 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_set_enabled_levels()
2490 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_nbps_index_settings() local
2496 if (pi->sys_info.nb_dpm_enable) { in kv_program_nbps_index_settings()
2550 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_sys_info_table() local
2567 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); in kv_parse_sys_info_table()
2568 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); in kv_parse_sys_info_table()
2569 pi->sys_info.bootup_nb_voltage_index = in kv_parse_sys_info_table()
2572 pi->sys_info.htc_tmp_lmt = 203; in kv_parse_sys_info_table()
2574 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; in kv_parse_sys_info_table()
2576 pi->sys_info.htc_hyst_lmt = 5; in kv_parse_sys_info_table()
2578 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; in kv_parse_sys_info_table()
2579 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { in kv_parse_sys_info_table()
2584 pi->sys_info.nb_dpm_enable = true; in kv_parse_sys_info_table()
2586 pi->sys_info.nb_dpm_enable = false; in kv_parse_sys_info_table()
2589 pi->sys_info.nbp_memory_clock[i] = in kv_parse_sys_info_table()
2591 pi->sys_info.nbp_n_clock[i] = in kv_parse_sys_info_table()
2596 pi->caps_enable_dfs_bypass = true; in kv_parse_sys_info_table()
2599 &pi->sys_info.sclk_voltage_mapping_table, in kv_parse_sys_info_table()
2603 &pi->sys_info.vid_mapping_table, in kv_parse_sys_info_table()
2636 struct kv_power_info *pi = kv_get_pi(adev); in kv_patch_boot_state() local
2639 ps->levels[0] = pi->boot_pl; in kv_patch_boot_state()
2673 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_pplib_clock_info() local
2685 if (pi->caps_sclk_ds) { in kv_parse_pplib_clock_info()
2781 struct kv_power_info *pi; in kv_dpm_init() local
2784 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); in kv_dpm_init()
2785 if (pi == NULL) in kv_dpm_init()
2787 adev->pm.dpm.priv = pi; in kv_dpm_init()
2798 pi->at[i] = TRINITY_AT_DFLT; in kv_dpm_init()
2800 pi->sram_end = SMC_RAM_END; in kv_dpm_init()
2802 pi->enable_nb_dpm = true; in kv_dpm_init()
2804 pi->caps_power_containment = true; in kv_dpm_init()
2805 pi->caps_cac = true; in kv_dpm_init()
2806 pi->enable_didt = false; in kv_dpm_init()
2807 if (pi->enable_didt) { in kv_dpm_init()
2808 pi->caps_sq_ramping = true; in kv_dpm_init()
2809 pi->caps_db_ramping = true; in kv_dpm_init()
2810 pi->caps_td_ramping = true; in kv_dpm_init()
2811 pi->caps_tcp_ramping = true; in kv_dpm_init()
2815 pi->caps_sclk_ds = true; in kv_dpm_init()
2817 pi->caps_sclk_ds = false; in kv_dpm_init()
2819 pi->enable_auto_thermal_throttling = true; in kv_dpm_init()
2820 pi->disable_nb_ps3_in_battery = false; in kv_dpm_init()
2822 pi->bapm_enable = false; in kv_dpm_init()
2824 pi->bapm_enable = true; in kv_dpm_init()
2825 pi->voltage_drop_t = 0; in kv_dpm_init()
2826 pi->caps_sclk_throttle_low_notification = false; in kv_dpm_init()
2827 pi->caps_fps = false; /* true? */ in kv_dpm_init()
2828 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false; in kv_dpm_init()
2829 pi->caps_uvd_dpm = true; in kv_dpm_init()
2830 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false; in kv_dpm_init()
2831 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false; in kv_dpm_init()
2832 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false; in kv_dpm_init()
2833 pi->caps_stable_p_state = false; in kv_dpm_init()
2846 pi->enable_dpm = true; in kv_dpm_init()
2856 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_debugfs_print_current_performance_level() local
2867 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_debugfs_print_current_performance_level()
2872 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2873 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2919 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_sclk() local
2920 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); in kv_dpm_get_sclk()
2931 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_mclk() local
2933 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_mclk()
3258 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_read_sensor() local
3273 pi->graphics_level[pl_index].SclkFrequency); in kv_dpm_read_sensor()