37 		((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
39 #define amdgpu_dpm_is_legacy_dpm(adev) ((adev)->powerplay.pp_handle == (adev))
43 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_sclk()
50 	ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle,  in amdgpu_dpm_get_sclk()
59 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_mclk()
66 	ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle,  in amdgpu_dpm_get_mclk()
76 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_powergating_by_smu()
98 				(adev)->powerplay.pp_handle, block_type, gate));  in amdgpu_dpm_set_powergating_by_smu()
114 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_set_gfx_power_up_by_imu()
128 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_baco_enter()
129 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_baco_enter()
147 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_baco_exit()
148 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_baco_exit()
168 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_mp1_state()
174 				adev->powerplay.pp_handle,  in amdgpu_dpm_set_mp1_state()
185 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_is_baco_supported()
186 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_is_baco_supported()
216 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_mode2_reset()
217 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_mode2_reset()
234 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_enable_gfx_features()
235 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_enable_gfx_features()
252 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_baco_reset()
253 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_baco_reset()
276 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_is_mode1_reset_supported()
290 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_mode1_reset()
306 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_switch_power_profile()
315 			adev->powerplay.pp_handle, type, en);  in amdgpu_dpm_switch_power_profile()
325 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_xgmi_pstate()
330 		ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,  in amdgpu_dpm_set_xgmi_pstate()
342 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_df_cstate()
343 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_set_df_cstate()
356 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_allow_xgmi_power_down()
370 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_enable_mgpu_fan_boost()
372 			adev->powerplay.pp_funcs;  in amdgpu_dpm_enable_mgpu_fan_boost()
387 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_set_clockgating_by_smu()
389 			adev->powerplay.pp_funcs;  in amdgpu_dpm_set_clockgating_by_smu()
405 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_smu_i2c_bus_access()
407 			adev->powerplay.pp_funcs;  in amdgpu_dpm_smu_i2c_bus_access()
429 		if (adev->powerplay.pp_funcs &&  in amdgpu_pm_acpi_event_handler()
430 		    adev->powerplay.pp_funcs->enable_bapm)  in amdgpu_pm_acpi_event_handler()
434 			smu_set_ac_dc(adev->powerplay.pp_handle);  in amdgpu_pm_acpi_event_handler()
443 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_read_sensor()
451 		ret = pp_funcs->read_sensor(adev->powerplay.pp_handle,  in amdgpu_dpm_read_sensor()
463 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_apu_thermal_limit()
468 		ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit);  in amdgpu_dpm_get_apu_thermal_limit()
477 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_apu_thermal_limit()
482 		ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit);  in amdgpu_dpm_set_apu_thermal_limit()
491 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_compute_clocks()
510 	pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle);  in amdgpu_dpm_compute_clocks()
575 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_pm_load_smu_firmware()
582 	r = pp_funcs->load_firmware(adev->powerplay.pp_handle);  in amdgpu_pm_load_smu_firmware()
602 		ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle,  in amdgpu_dpm_handle_passthrough_sbr()
612 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_send_hbm_bad_pages_num()
627 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_send_hbm_bad_channel_flag()
654 	ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle,  in amdgpu_dpm_get_dpm_freq_range()
668 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_set_soft_freq_range()
689 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_write_watermarks_table()
706 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_wait_for_event()
721 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_set_residency_gfxoff()
736 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_get_residency_gfxoff()
751 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_get_entrycount_gfxoff()
766 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_get_status_gfxoff()
781 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_get_thermal_throttling_counter()
798 	if (adev->powerplay.pp_funcs &&  in amdgpu_dpm_gfx_state_change()
799 	    adev->powerplay.pp_funcs->gfx_state_change_set)  in amdgpu_dpm_gfx_state_change()
800 		((adev)->powerplay.pp_funcs->gfx_state_change_set(  in amdgpu_dpm_gfx_state_change()
801 			(adev)->powerplay.pp_handle, state));  in amdgpu_dpm_gfx_state_change()
808 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_get_ecc_info()
824 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_vce_clock_state()
831 	vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle,  in amdgpu_dpm_get_vce_clock_state()
841 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_current_power_state()
850 	*state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle);  in amdgpu_dpm_get_current_power_state()
877 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_performance_level()
885 		level = pp_funcs->get_performance_level(adev->powerplay.pp_handle);  in amdgpu_dpm_get_performance_level()
896 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_force_performance_level()
950 	if (pp_funcs->force_performance_level(adev->powerplay.pp_handle,  in amdgpu_dpm_force_performance_level()
966 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_pp_num_states()
973 	ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle,  in amdgpu_dpm_get_pp_num_states()
984 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_dispatch_task()
991 	ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle,  in amdgpu_dpm_dispatch_task()
1001 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_pp_table()
1008 	ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle,  in amdgpu_dpm_get_pp_table()
1020 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_fine_grain_clk_vol()
1027 	ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle,  in amdgpu_dpm_set_fine_grain_clk_vol()
1041 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_odn_edit_dpm_table()
1048 	ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle,  in amdgpu_dpm_odn_edit_dpm_table()
1061 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_print_clock_levels()
1068 	ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle,  in amdgpu_dpm_print_clock_levels()
1081 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_emit_clock_levels()
1088 	ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle,  in amdgpu_dpm_emit_clock_levels()
1100 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_ppfeature_status()
1107 	ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle,  in amdgpu_dpm_set_ppfeature_status()
1116 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_ppfeature_status()
1123 	ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle,  in amdgpu_dpm_get_ppfeature_status()
1134 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_force_clock_level()
1141 	ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle,  in amdgpu_dpm_force_clock_level()
1151 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_sclk_od()
1158 	ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle);  in amdgpu_dpm_get_sclk_od()
1166 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_sclk_od()
1173 		pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value);  in amdgpu_dpm_set_sclk_od()
1188 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_mclk_od()
1195 	ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle);  in amdgpu_dpm_get_mclk_od()
1203 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_mclk_od()
1210 		pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value);  in amdgpu_dpm_set_mclk_od()
1226 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_power_profile_mode()
1233 	ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle,  in amdgpu_dpm_get_power_profile_mode()
1243 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_power_profile_mode()
1250 	ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle,  in amdgpu_dpm_set_power_profile_mode()
1260 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_gpu_metrics()
1267 	ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle,  in amdgpu_dpm_get_gpu_metrics()
1277 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_fan_control_mode()
1284 	ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle,  in amdgpu_dpm_get_fan_control_mode()
1294 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_fan_speed_pwm()
1301 	ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle,  in amdgpu_dpm_set_fan_speed_pwm()
1311 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_fan_speed_pwm()
1318 	ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle,  in amdgpu_dpm_get_fan_speed_pwm()
1328 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_fan_speed_rpm()
1335 	ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle,  in amdgpu_dpm_get_fan_speed_rpm()
1345 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_fan_speed_rpm()
1352 	ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle,  in amdgpu_dpm_set_fan_speed_rpm()
1362 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_fan_control_mode()
1369 	ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle,  in amdgpu_dpm_set_fan_control_mode()
1381 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_power_limit()
1388 	ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle,  in amdgpu_dpm_get_power_limit()
1400 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_power_limit()
1407 	ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle,  in amdgpu_dpm_set_power_limit()
1431 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_debugfs_print_current_performance_level()
1437 	pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle,  in amdgpu_dpm_debugfs_print_current_performance_level()
1448 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_smu_prv_buf_details()
1455 	ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle,  in amdgpu_dpm_get_smu_prv_buf_details()
1466 		struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_is_overdrive_supported()
1479 		hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle;  in amdgpu_dpm_is_overdrive_supported()
1489 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_pp_table()
1496 	ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle,  in amdgpu_dpm_set_pp_table()
1506 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_get_num_cpu_cores()
1525 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_display_configuration_change()
1532 	ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle,  in amdgpu_dpm_display_configuration_change()
1543 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_clock_by_type()
1550 	ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle,  in amdgpu_dpm_get_clock_by_type()
1561 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_display_mode_validation_clks()
1568 	ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle,  in amdgpu_dpm_get_display_mode_validation_clks()
1579 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_clock_by_type_with_latency()
1586 	ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle,  in amdgpu_dpm_get_clock_by_type_with_latency()
1598 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_clock_by_type_with_voltage()
1605 	ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle,  in amdgpu_dpm_get_clock_by_type_with_voltage()
1616 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1623 	ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle,  in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1633 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_display_clock_voltage_request()
1640 	ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle,  in amdgpu_dpm_display_clock_voltage_request()
1650 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_current_clocks()
1657 	ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle,  in amdgpu_dpm_get_current_clocks()
1666 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_notify_smu_enable_pwe()
1672 	pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle);  in amdgpu_dpm_notify_smu_enable_pwe()
1679 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_active_display_count()
1686 	ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle,  in amdgpu_dpm_set_active_display_count()
1696 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1703 	ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle,  in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1713 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1719 	pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle,  in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1727 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_hard_min_fclk_by_freq()
1733 	pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle,  in amdgpu_dpm_set_hard_min_fclk_by_freq()
1741 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_display_disable_memory_clock_switch()
1748 	ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle,  in amdgpu_dpm_display_disable_memory_clock_switch()
1758 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1765 	ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle,  in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1776 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_uclk_dpm_states()
1783 	ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle,  in amdgpu_dpm_get_uclk_dpm_states()
1794 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_dpm_clock_table()
1801 	ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle,  in amdgpu_dpm_get_dpm_clock_table()