Lines Matching refs:adev
36 #define amdgpu_dpm_enable_bapm(adev, e) \ argument
37 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
39 #define amdgpu_dpm_is_legacy_dpm(adev) ((adev)->powerplay.pp_handle == (adev)) argument
41 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) in amdgpu_dpm_get_sclk() argument
43 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_sclk()
49 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_sclk()
50 ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, in amdgpu_dpm_get_sclk()
52 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_sclk()
57 int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) in amdgpu_dpm_get_mclk() argument
59 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_mclk()
65 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_mclk()
66 ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, in amdgpu_dpm_get_mclk()
68 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_mclk()
73 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) in amdgpu_dpm_set_powergating_by_smu() argument
76 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_powergating_by_smu()
79 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) { in amdgpu_dpm_set_powergating_by_smu()
80 dev_dbg(adev->dev, "IP block%d already in the target %s state!", in amdgpu_dpm_set_powergating_by_smu()
85 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
98 (adev)->powerplay.pp_handle, block_type, gate)); in amdgpu_dpm_set_powergating_by_smu()
105 atomic_set(&adev->pm.pwr_state[block_type], pwr_state); in amdgpu_dpm_set_powergating_by_smu()
107 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
112 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) in amdgpu_dpm_set_gfx_power_up_by_imu() argument
114 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_gfx_power_up_by_imu()
117 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_gfx_power_up_by_imu()
119 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_gfx_power_up_by_imu()
126 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) in amdgpu_dpm_baco_enter() argument
128 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_enter()
129 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_enter()
135 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_baco_enter()
140 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_baco_enter()
145 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) in amdgpu_dpm_baco_exit() argument
147 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_exit()
148 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_exit()
154 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_baco_exit()
159 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_baco_exit()
164 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, in amdgpu_dpm_set_mp1_state() argument
168 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_mp1_state()
171 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_mp1_state()
174 adev->powerplay.pp_handle, in amdgpu_dpm_set_mp1_state()
177 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_mp1_state()
183 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_baco_supported() argument
185 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_is_baco_supported()
186 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_is_baco_supported()
201 if (adev->in_s3) in amdgpu_dpm_is_baco_supported()
204 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_is_baco_supported()
209 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_is_baco_supported()
214 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) in amdgpu_dpm_mode2_reset() argument
216 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_mode2_reset()
217 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_mode2_reset()
223 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_mode2_reset()
227 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_mode2_reset()
232 int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) in amdgpu_dpm_enable_gfx_features() argument
234 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_enable_gfx_features()
235 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_enable_gfx_features()
241 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_gfx_features()
245 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_gfx_features()
250 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) in amdgpu_dpm_baco_reset() argument
252 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_reset()
253 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_reset()
259 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_baco_reset()
270 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_baco_reset()
274 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_mode1_reset_supported() argument
276 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_is_mode1_reset_supported()
279 if (is_support_sw_smu(adev)) { in amdgpu_dpm_is_mode1_reset_supported()
280 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_is_mode1_reset_supported()
282 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_is_mode1_reset_supported()
288 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) in amdgpu_dpm_mode1_reset() argument
290 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_mode1_reset()
293 if (is_support_sw_smu(adev)) { in amdgpu_dpm_mode1_reset()
294 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_mode1_reset()
296 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_mode1_reset()
302 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, in amdgpu_dpm_switch_power_profile() argument
306 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_switch_power_profile()
309 if (amdgpu_sriov_vf(adev)) in amdgpu_dpm_switch_power_profile()
313 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_switch_power_profile()
315 adev->powerplay.pp_handle, type, en); in amdgpu_dpm_switch_power_profile()
316 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_switch_power_profile()
322 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, in amdgpu_dpm_set_xgmi_pstate() argument
325 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_xgmi_pstate()
329 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_xgmi_pstate()
330 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, in amdgpu_dpm_set_xgmi_pstate()
332 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_xgmi_pstate()
338 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, in amdgpu_dpm_set_df_cstate() argument
342 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_df_cstate()
343 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_df_cstate()
346 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_df_cstate()
348 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_df_cstate()
354 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en) in amdgpu_dpm_allow_xgmi_power_down() argument
356 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_allow_xgmi_power_down()
359 if (is_support_sw_smu(adev)) { in amdgpu_dpm_allow_xgmi_power_down()
360 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_allow_xgmi_power_down()
362 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_allow_xgmi_power_down()
368 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) in amdgpu_dpm_enable_mgpu_fan_boost() argument
370 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_enable_mgpu_fan_boost()
372 adev->powerplay.pp_funcs; in amdgpu_dpm_enable_mgpu_fan_boost()
376 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_mgpu_fan_boost()
378 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_mgpu_fan_boost()
384 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, in amdgpu_dpm_set_clockgating_by_smu() argument
387 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_clockgating_by_smu()
389 adev->powerplay.pp_funcs; in amdgpu_dpm_set_clockgating_by_smu()
393 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_clockgating_by_smu()
396 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_clockgating_by_smu()
402 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, in amdgpu_dpm_smu_i2c_bus_access() argument
405 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_smu_i2c_bus_access()
407 adev->powerplay.pp_funcs; in amdgpu_dpm_smu_i2c_bus_access()
411 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_smu_i2c_bus_access()
414 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_smu_i2c_bus_access()
420 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) in amdgpu_pm_acpi_event_handler() argument
422 if (adev->pm.dpm_enabled) { in amdgpu_pm_acpi_event_handler()
423 mutex_lock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
425 adev->pm.ac_power = true; in amdgpu_pm_acpi_event_handler()
427 adev->pm.ac_power = false; in amdgpu_pm_acpi_event_handler()
429 if (adev->powerplay.pp_funcs && in amdgpu_pm_acpi_event_handler()
430 adev->powerplay.pp_funcs->enable_bapm) in amdgpu_pm_acpi_event_handler()
431 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); in amdgpu_pm_acpi_event_handler()
433 if (is_support_sw_smu(adev)) in amdgpu_pm_acpi_event_handler()
434 smu_set_ac_dc(adev->powerplay.pp_handle); in amdgpu_pm_acpi_event_handler()
436 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
440 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, in amdgpu_dpm_read_sensor() argument
443 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_read_sensor()
450 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_read_sensor()
451 ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, in amdgpu_dpm_read_sensor()
455 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_read_sensor()
461 int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit) in amdgpu_dpm_get_apu_thermal_limit() argument
463 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_apu_thermal_limit()
467 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_apu_thermal_limit()
468 ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); in amdgpu_dpm_get_apu_thermal_limit()
469 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_apu_thermal_limit()
475 int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) in amdgpu_dpm_set_apu_thermal_limit() argument
477 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_apu_thermal_limit()
481 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_apu_thermal_limit()
482 ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); in amdgpu_dpm_set_apu_thermal_limit()
483 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_apu_thermal_limit()
489 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) in amdgpu_dpm_compute_clocks() argument
491 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_compute_clocks()
494 if (!adev->pm.dpm_enabled) in amdgpu_dpm_compute_clocks()
500 if (adev->mode_info.num_crtc) in amdgpu_dpm_compute_clocks()
501 amdgpu_display_bandwidth_update(adev); in amdgpu_dpm_compute_clocks()
504 struct amdgpu_ring *ring = adev->rings[i]; in amdgpu_dpm_compute_clocks()
509 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_compute_clocks()
510 pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); in amdgpu_dpm_compute_clocks()
511 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_compute_clocks()
514 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_uvd() argument
518 if (adev->family == AMDGPU_FAMILY_SI) { in amdgpu_dpm_enable_uvd()
519 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
521 adev->pm.dpm.uvd_active = true; in amdgpu_dpm_enable_uvd()
522 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; in amdgpu_dpm_enable_uvd()
524 adev->pm.dpm.uvd_active = false; in amdgpu_dpm_enable_uvd()
526 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
528 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_enable_uvd()
532 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable); in amdgpu_dpm_enable_uvd()
538 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_vce() argument
542 if (adev->family == AMDGPU_FAMILY_SI) { in amdgpu_dpm_enable_vce()
543 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
545 adev->pm.dpm.vce_active = true; in amdgpu_dpm_enable_vce()
547 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; in amdgpu_dpm_enable_vce()
549 adev->pm.dpm.vce_active = false; in amdgpu_dpm_enable_vce()
551 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
553 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_enable_vce()
557 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable); in amdgpu_dpm_enable_vce()
563 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_jpeg() argument
567 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable); in amdgpu_dpm_enable_jpeg()
573 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) in amdgpu_pm_load_smu_firmware() argument
575 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_pm_load_smu_firmware()
581 mutex_lock(&adev->pm.mutex); in amdgpu_pm_load_smu_firmware()
582 r = pp_funcs->load_firmware(adev->powerplay.pp_handle); in amdgpu_pm_load_smu_firmware()
589 *smu_version = adev->pm.fw_version; in amdgpu_pm_load_smu_firmware()
592 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_load_smu_firmware()
596 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_handle_passthrough_sbr() argument
600 if (is_support_sw_smu(adev)) { in amdgpu_dpm_handle_passthrough_sbr()
601 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_handle_passthrough_sbr()
602 ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, in amdgpu_dpm_handle_passthrough_sbr()
604 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_handle_passthrough_sbr()
610 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) in amdgpu_dpm_send_hbm_bad_pages_num() argument
612 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_send_hbm_bad_pages_num()
615 if (!is_support_sw_smu(adev)) in amdgpu_dpm_send_hbm_bad_pages_num()
618 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_pages_num()
620 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_pages_num()
625 int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) in amdgpu_dpm_send_hbm_bad_channel_flag() argument
627 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_send_hbm_bad_channel_flag()
630 if (!is_support_sw_smu(adev)) in amdgpu_dpm_send_hbm_bad_channel_flag()
633 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_channel_flag()
635 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_channel_flag()
640 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, in amdgpu_dpm_get_dpm_freq_range() argument
650 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_dpm_freq_range()
653 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_freq_range()
654 ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, in amdgpu_dpm_get_dpm_freq_range()
658 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_freq_range()
663 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, in amdgpu_dpm_set_soft_freq_range() argument
668 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_soft_freq_range()
674 if (!is_support_sw_smu(adev)) in amdgpu_dpm_set_soft_freq_range()
677 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_soft_freq_range()
682 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_soft_freq_range()
687 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) in amdgpu_dpm_write_watermarks_table() argument
689 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_write_watermarks_table()
692 if (!is_support_sw_smu(adev)) in amdgpu_dpm_write_watermarks_table()
695 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_write_watermarks_table()
697 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_write_watermarks_table()
702 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, in amdgpu_dpm_wait_for_event() argument
706 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_wait_for_event()
709 if (!is_support_sw_smu(adev)) in amdgpu_dpm_wait_for_event()
712 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_wait_for_event()
714 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_wait_for_event()
719 int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) in amdgpu_dpm_set_residency_gfxoff() argument
721 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_residency_gfxoff()
724 if (!is_support_sw_smu(adev)) in amdgpu_dpm_set_residency_gfxoff()
727 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_residency_gfxoff()
729 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_residency_gfxoff()
734 int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) in amdgpu_dpm_get_residency_gfxoff() argument
736 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_residency_gfxoff()
739 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_residency_gfxoff()
742 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_residency_gfxoff()
744 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_residency_gfxoff()
749 int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) in amdgpu_dpm_get_entrycount_gfxoff() argument
751 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_entrycount_gfxoff()
754 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_entrycount_gfxoff()
757 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_entrycount_gfxoff()
759 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_entrycount_gfxoff()
764 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) in amdgpu_dpm_get_status_gfxoff() argument
766 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_status_gfxoff()
769 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_status_gfxoff()
772 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_status_gfxoff()
774 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_status_gfxoff()
779 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) in amdgpu_dpm_get_thermal_throttling_counter() argument
781 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_thermal_throttling_counter()
783 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_thermal_throttling_counter()
794 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, in amdgpu_dpm_gfx_state_change() argument
797 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_gfx_state_change()
798 if (adev->powerplay.pp_funcs && in amdgpu_dpm_gfx_state_change()
799 adev->powerplay.pp_funcs->gfx_state_change_set) in amdgpu_dpm_gfx_state_change()
800 ((adev)->powerplay.pp_funcs->gfx_state_change_set( in amdgpu_dpm_gfx_state_change()
801 (adev)->powerplay.pp_handle, state)); in amdgpu_dpm_gfx_state_change()
802 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_gfx_state_change()
805 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, in amdgpu_dpm_get_ecc_info() argument
808 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_ecc_info()
811 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_ecc_info()
814 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_ecc_info()
816 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_ecc_info()
821 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, in amdgpu_dpm_get_vce_clock_state() argument
824 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_vce_clock_state()
830 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_vce_clock_state()
831 vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, in amdgpu_dpm_get_vce_clock_state()
833 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_vce_clock_state()
838 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, in amdgpu_dpm_get_current_power_state() argument
841 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_current_power_state()
843 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_current_power_state()
846 *state = adev->pm.dpm.user_state; in amdgpu_dpm_get_current_power_state()
850 *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); in amdgpu_dpm_get_current_power_state()
853 *state = adev->pm.dpm.user_state; in amdgpu_dpm_get_current_power_state()
856 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_current_power_state()
859 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, in amdgpu_dpm_set_power_state() argument
862 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_power_state()
863 adev->pm.dpm.user_state = state; in amdgpu_dpm_set_power_state()
864 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_power_state()
866 if (is_support_sw_smu(adev)) in amdgpu_dpm_set_power_state()
869 if (amdgpu_dpm_dispatch_task(adev, in amdgpu_dpm_set_power_state()
872 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_set_power_state()
875 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev) in amdgpu_dpm_get_performance_level() argument
877 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_performance_level()
883 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_performance_level()
885 level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); in amdgpu_dpm_get_performance_level()
887 level = adev->pm.dpm.forced_level; in amdgpu_dpm_get_performance_level()
888 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_performance_level()
893 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, in amdgpu_dpm_force_performance_level() argument
896 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_force_performance_level()
906 if (adev->pm.dpm.thermal_active) in amdgpu_dpm_force_performance_level()
909 current_level = amdgpu_dpm_get_performance_level(adev); in amdgpu_dpm_force_performance_level()
913 if (adev->asic_type == CHIP_RAVEN) { in amdgpu_dpm_force_performance_level()
914 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) { in amdgpu_dpm_force_performance_level()
917 amdgpu_gfx_off_ctrl(adev, false); in amdgpu_dpm_force_performance_level()
920 amdgpu_gfx_off_ctrl(adev, true); in amdgpu_dpm_force_performance_level()
931 amdgpu_device_ip_set_powergating_state(adev, in amdgpu_dpm_force_performance_level()
934 amdgpu_device_ip_set_clockgating_state(adev, in amdgpu_dpm_force_performance_level()
940 amdgpu_device_ip_set_clockgating_state(adev, in amdgpu_dpm_force_performance_level()
943 amdgpu_device_ip_set_powergating_state(adev, in amdgpu_dpm_force_performance_level()
948 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_force_performance_level()
950 if (pp_funcs->force_performance_level(adev->powerplay.pp_handle, in amdgpu_dpm_force_performance_level()
952 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_force_performance_level()
956 adev->pm.dpm.forced_level = level; in amdgpu_dpm_force_performance_level()
958 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_force_performance_level()
963 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, in amdgpu_dpm_get_pp_num_states() argument
966 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_pp_num_states()
972 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_pp_num_states()
973 ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, in amdgpu_dpm_get_pp_num_states()
975 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_pp_num_states()
980 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, in amdgpu_dpm_dispatch_task() argument
984 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_dispatch_task()
990 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_dispatch_task()
991 ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, in amdgpu_dpm_dispatch_task()
994 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_dispatch_task()
999 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) in amdgpu_dpm_get_pp_table() argument
1001 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_pp_table()
1007 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_pp_table()
1008 ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, in amdgpu_dpm_get_pp_table()
1010 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_pp_table()
1015 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, in amdgpu_dpm_set_fine_grain_clk_vol() argument
1020 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fine_grain_clk_vol()
1026 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fine_grain_clk_vol()
1027 ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, in amdgpu_dpm_set_fine_grain_clk_vol()
1031 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fine_grain_clk_vol()
1036 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, in amdgpu_dpm_odn_edit_dpm_table() argument
1041 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_odn_edit_dpm_table()
1047 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_odn_edit_dpm_table()
1048 ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, in amdgpu_dpm_odn_edit_dpm_table()
1052 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_odn_edit_dpm_table()
1057 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, in amdgpu_dpm_print_clock_levels() argument
1061 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_print_clock_levels()
1067 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_print_clock_levels()
1068 ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle, in amdgpu_dpm_print_clock_levels()
1071 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_print_clock_levels()
1076 int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, in amdgpu_dpm_emit_clock_levels() argument
1081 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_emit_clock_levels()
1087 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_emit_clock_levels()
1088 ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, in amdgpu_dpm_emit_clock_levels()
1092 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_emit_clock_levels()
1097 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, in amdgpu_dpm_set_ppfeature_status() argument
1100 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_ppfeature_status()
1106 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_ppfeature_status()
1107 ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, in amdgpu_dpm_set_ppfeature_status()
1109 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_ppfeature_status()
1114 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) in amdgpu_dpm_get_ppfeature_status() argument
1116 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_ppfeature_status()
1122 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_ppfeature_status()
1123 ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, in amdgpu_dpm_get_ppfeature_status()
1125 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_ppfeature_status()
1130 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, in amdgpu_dpm_force_clock_level() argument
1134 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_force_clock_level()
1140 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_force_clock_level()
1141 ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, in amdgpu_dpm_force_clock_level()
1144 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_force_clock_level()
1149 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) in amdgpu_dpm_get_sclk_od() argument
1151 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_sclk_od()
1157 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_sclk_od()
1158 ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); in amdgpu_dpm_get_sclk_od()
1159 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_sclk_od()
1164 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) in amdgpu_dpm_set_sclk_od() argument
1166 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_sclk_od()
1168 if (is_support_sw_smu(adev)) in amdgpu_dpm_set_sclk_od()
1171 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_sclk_od()
1173 pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); in amdgpu_dpm_set_sclk_od()
1174 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_sclk_od()
1176 if (amdgpu_dpm_dispatch_task(adev, in amdgpu_dpm_set_sclk_od()
1179 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; in amdgpu_dpm_set_sclk_od()
1180 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_set_sclk_od()
1186 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) in amdgpu_dpm_get_mclk_od() argument
1188 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_mclk_od()
1194 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_mclk_od()
1195 ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); in amdgpu_dpm_get_mclk_od()
1196 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_mclk_od()
1201 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) in amdgpu_dpm_set_mclk_od() argument
1203 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_mclk_od()
1205 if (is_support_sw_smu(adev)) in amdgpu_dpm_set_mclk_od()
1208 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_mclk_od()
1210 pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); in amdgpu_dpm_set_mclk_od()
1211 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_mclk_od()
1213 if (amdgpu_dpm_dispatch_task(adev, in amdgpu_dpm_set_mclk_od()
1216 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; in amdgpu_dpm_set_mclk_od()
1217 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_set_mclk_od()
1223 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, in amdgpu_dpm_get_power_profile_mode() argument
1226 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_power_profile_mode()
1232 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_power_profile_mode()
1233 ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, in amdgpu_dpm_get_power_profile_mode()
1235 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_power_profile_mode()
1240 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, in amdgpu_dpm_set_power_profile_mode() argument
1243 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_power_profile_mode()
1249 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_power_profile_mode()
1250 ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, in amdgpu_dpm_set_power_profile_mode()
1253 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_power_profile_mode()
1258 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) in amdgpu_dpm_get_gpu_metrics() argument
1260 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_gpu_metrics()
1266 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_gpu_metrics()
1267 ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, in amdgpu_dpm_get_gpu_metrics()
1269 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_gpu_metrics()
1274 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, in amdgpu_dpm_get_fan_control_mode() argument
1277 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_fan_control_mode()
1283 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_fan_control_mode()
1284 ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, in amdgpu_dpm_get_fan_control_mode()
1286 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_fan_control_mode()
1291 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, in amdgpu_dpm_set_fan_speed_pwm() argument
1294 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fan_speed_pwm()
1300 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_pwm()
1301 ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, in amdgpu_dpm_set_fan_speed_pwm()
1303 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_pwm()
1308 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, in amdgpu_dpm_get_fan_speed_pwm() argument
1311 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_fan_speed_pwm()
1317 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_pwm()
1318 ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, in amdgpu_dpm_get_fan_speed_pwm()
1320 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_pwm()
1325 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, in amdgpu_dpm_get_fan_speed_rpm() argument
1328 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_fan_speed_rpm()
1334 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_rpm()
1335 ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, in amdgpu_dpm_get_fan_speed_rpm()
1337 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_rpm()
1342 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, in amdgpu_dpm_set_fan_speed_rpm() argument
1345 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fan_speed_rpm()
1351 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_rpm()
1352 ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, in amdgpu_dpm_set_fan_speed_rpm()
1354 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_rpm()
1359 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, in amdgpu_dpm_set_fan_control_mode() argument
1362 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fan_control_mode()
1368 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fan_control_mode()
1369 ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, in amdgpu_dpm_set_fan_control_mode()
1371 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fan_control_mode()
1376 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, in amdgpu_dpm_get_power_limit() argument
1381 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_power_limit()
1387 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_power_limit()
1388 ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, in amdgpu_dpm_get_power_limit()
1392 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_power_limit()
1397 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, in amdgpu_dpm_set_power_limit() argument
1400 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_power_limit()
1406 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_power_limit()
1407 ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, in amdgpu_dpm_set_power_limit()
1409 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_power_limit()
1414 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_cclk_dpm_supported() argument
1418 if (!is_support_sw_smu(adev)) in amdgpu_dpm_is_cclk_dpm_supported()
1421 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_is_cclk_dpm_supported()
1422 cclk_dpm_supported = is_support_cclk_dpm(adev); in amdgpu_dpm_is_cclk_dpm_supported()
1423 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_is_cclk_dpm_supported()
1428 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, in amdgpu_dpm_debugfs_print_current_performance_level() argument
1431 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_debugfs_print_current_performance_level()
1436 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_debugfs_print_current_performance_level()
1437 pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, in amdgpu_dpm_debugfs_print_current_performance_level()
1439 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_debugfs_print_current_performance_level()
1444 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, in amdgpu_dpm_get_smu_prv_buf_details() argument
1448 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_smu_prv_buf_details()
1454 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_smu_prv_buf_details()
1455 ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, in amdgpu_dpm_get_smu_prv_buf_details()
1458 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_smu_prv_buf_details()
1463 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_overdrive_supported() argument
1465 if (is_support_sw_smu(adev)) { in amdgpu_dpm_is_overdrive_supported()
1466 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_is_overdrive_supported()
1476 if (amdgpu_dpm_is_legacy_dpm(adev)) in amdgpu_dpm_is_overdrive_supported()
1479 hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle; in amdgpu_dpm_is_overdrive_supported()
1485 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, in amdgpu_dpm_set_pp_table() argument
1489 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_pp_table()
1495 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_pp_table()
1496 ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, in amdgpu_dpm_set_pp_table()
1499 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_pp_table()
1504 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) in amdgpu_dpm_get_num_cpu_cores() argument
1506 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_num_cpu_cores()
1508 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_num_cpu_cores()
1514 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev) in amdgpu_dpm_stb_debug_fs_init() argument
1516 if (!is_support_sw_smu(adev)) in amdgpu_dpm_stb_debug_fs_init()
1519 amdgpu_smu_stb_debug_fs_init(adev); in amdgpu_dpm_stb_debug_fs_init()
1522 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, in amdgpu_dpm_display_configuration_change() argument
1525 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_display_configuration_change()
1531 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_display_configuration_change()
1532 ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, in amdgpu_dpm_display_configuration_change()
1534 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_display_configuration_change()
1539 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, in amdgpu_dpm_get_clock_by_type() argument
1543 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_clock_by_type()
1549 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type()
1550 ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, in amdgpu_dpm_get_clock_by_type()
1553 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type()
1558 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, in amdgpu_dpm_get_display_mode_validation_clks() argument
1561 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_display_mode_validation_clks()
1567 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_display_mode_validation_clks()
1568 ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, in amdgpu_dpm_get_display_mode_validation_clks()
1570 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_display_mode_validation_clks()
1575 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, in amdgpu_dpm_get_clock_by_type_with_latency() argument
1579 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_clock_by_type_with_latency()
1585 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_latency()
1586 ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, in amdgpu_dpm_get_clock_by_type_with_latency()
1589 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_latency()
1594 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, in amdgpu_dpm_get_clock_by_type_with_voltage() argument
1598 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_clock_by_type_with_voltage()
1604 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_voltage()
1605 ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, in amdgpu_dpm_get_clock_by_type_with_voltage()
1608 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_voltage()
1613 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, in amdgpu_dpm_set_watermarks_for_clocks_ranges() argument
1616 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1622 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1623 ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1625 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1630 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, in amdgpu_dpm_display_clock_voltage_request() argument
1633 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_display_clock_voltage_request()
1639 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_display_clock_voltage_request()
1640 ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, in amdgpu_dpm_display_clock_voltage_request()
1642 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_display_clock_voltage_request()
1647 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, in amdgpu_dpm_get_current_clocks() argument
1650 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_current_clocks()
1656 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_current_clocks()
1657 ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, in amdgpu_dpm_get_current_clocks()
1659 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_current_clocks()
1664 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) in amdgpu_dpm_notify_smu_enable_pwe() argument
1666 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_notify_smu_enable_pwe()
1671 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_notify_smu_enable_pwe()
1672 pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); in amdgpu_dpm_notify_smu_enable_pwe()
1673 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_notify_smu_enable_pwe()
1676 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, in amdgpu_dpm_set_active_display_count() argument
1679 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_active_display_count()
1685 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_active_display_count()
1686 ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, in amdgpu_dpm_set_active_display_count()
1688 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_active_display_count()
1693 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, in amdgpu_dpm_set_min_deep_sleep_dcefclk() argument
1696 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1702 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1703 ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1705 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1710 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, in amdgpu_dpm_set_hard_min_dcefclk_by_freq() argument
1713 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1718 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1719 pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1721 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1724 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, in amdgpu_dpm_set_hard_min_fclk_by_freq() argument
1727 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_hard_min_fclk_by_freq()
1732 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_fclk_by_freq()
1733 pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, in amdgpu_dpm_set_hard_min_fclk_by_freq()
1735 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_fclk_by_freq()
1738 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, in amdgpu_dpm_display_disable_memory_clock_switch() argument
1741 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_display_disable_memory_clock_switch()
1747 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_display_disable_memory_clock_switch()
1748 ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, in amdgpu_dpm_display_disable_memory_clock_switch()
1750 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_display_disable_memory_clock_switch()
1755 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, in amdgpu_dpm_get_max_sustainable_clocks_by_dc() argument
1758 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1764 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1765 ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1767 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1772 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, in amdgpu_dpm_get_uclk_dpm_states() argument
1776 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_uclk_dpm_states()
1782 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_uclk_dpm_states()
1783 ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, in amdgpu_dpm_get_uclk_dpm_states()
1786 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_uclk_dpm_states()
1791 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, in amdgpu_dpm_get_dpm_clock_table() argument
1794 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_dpm_clock_table()
1800 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_clock_table()
1801 ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, in amdgpu_dpm_get_dpm_clock_table()
1803 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_clock_table()