Lines Matching refs:uint32_t
51 uint32_t vmid;
52 uint32_t mc_id;
53 uint32_t status;
61 uint32_t num_shader_engines;
62 uint32_t num_shader_arrays_per_engine;
63 uint32_t num_cu_per_sh;
64 uint32_t cu_active_number;
65 uint32_t cu_ao_mask;
66 uint32_t simd_per_cu;
67 uint32_t max_waves_per_simd;
68 uint32_t wave_front_size;
69 uint32_t max_scratch_slots_per_cu;
70 uint32_t lds_size;
71 uint32_t cu_bitmap[AMDGPU_MAX_GC_INSTANCES][4][4];
78 uint32_t vram_width;
79 uint32_t mem_clk_max;
120 uint32_t num_pipe_per_mec;
123 uint32_t num_queue_per_pipe;
132 uint32_t *sdma_doorbell_idx;
137 uint32_t non_cp_doorbells_start;
138 uint32_t non_cp_doorbells_end;
159 uint32_t *tile_config_ptr;
160 uint32_t *macro_tile_config_ptr;
161 uint32_t num_tile_configs;
162 uint32_t num_macro_tile_configs;
164 uint32_t gb_addr_config;
165 uint32_t num_banks;
166 uint32_t num_ranks;
231 void (*program_sh_mem_settings)(struct amdgpu_device *adev, uint32_t vmid,
232 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
233 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases,
234 uint32_t inst);
237 unsigned int vmid, uint32_t inst);
239 int (*init_interrupts)(struct amdgpu_device *adev, uint32_t pipe_id,
240 uint32_t inst);
242 int (*hqd_load)(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,
243 uint32_t queue_id, uint32_t __user *wptr,
244 uint32_t wptr_shift, uint32_t wptr_mask,
245 struct mm_struct *mm, uint32_t inst);
248 uint32_t pipe_id, uint32_t queue_id,
249 uint32_t doorbell_off, uint32_t inst);
252 uint32_t __user *wptr, struct mm_struct *mm);
255 uint32_t pipe_id, uint32_t queue_id,
256 uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst);
259 uint32_t engine_id, uint32_t queue_id,
260 uint32_t (**dump)[2], uint32_t *n_regs);
263 uint64_t queue_address, uint32_t pipe_id,
264 uint32_t queue_id, uint32_t inst);
268 unsigned int timeout, uint32_t pipe_id,
269 uint32_t queue_id, uint32_t inst);
277 uint32_t gfx_index_val,
278 uint32_t sq_cmd, uint32_t inst);
288 uint64_t va, uint32_t vmid);
291 uint32_t vmid, uint64_t page_table_base);
292 uint32_t (*read_vmid_from_vmfault_reg)(struct amdgpu_device *adev);
294 uint32_t (*enable_debug_trap)(struct amdgpu_device *adev,
296 uint32_t vmid);
297 uint32_t (*disable_debug_trap)(struct amdgpu_device *adev,
299 uint32_t vmid);
301 uint32_t trap_override,
302 uint32_t *trap_mask_supported);
303 uint32_t (*set_wave_launch_trap_override)(struct amdgpu_device *adev,
304 uint32_t vmid,
305 uint32_t trap_override,
306 uint32_t trap_mask_bits,
307 uint32_t trap_mask_request,
308 uint32_t *trap_mask_prev,
309 uint32_t kfd_dbg_trap_cntl_prev);
310 uint32_t (*set_wave_launch_mode)(struct amdgpu_device *adev,
312 uint32_t vmid);
313 uint32_t (*set_address_watch)(struct amdgpu_device *adev,
315 uint32_t watch_address_mask,
316 uint32_t watch_id,
317 uint32_t watch_mode,
318 uint32_t debug_vmid,
319 uint32_t inst);
320 uint32_t (*clear_address_watch)(struct amdgpu_device *adev,
321 uint32_t watch_id);
323 uint32_t *wait_times,
324 uint32_t inst);
326 uint32_t wait_times,
327 uint32_t grace_period,
328 uint32_t *reg_offset,
329 uint32_t *reg_data);
331 int *wave_cnt, int *max_waves_per_cu, uint32_t inst);
333 uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,
334 uint32_t inst);