Lines Matching refs:uint8_t
52 #ifndef uint8_t
53 typedef unsigned char uint8_t; typedef
235 …uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compa…
236 …uint8_t content_revision; //change it when a data table has a structure change, or a hw function…
245 …uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to d…
448 uint8_t h_border;
449 uint8_t v_border;
451 uint8_t atom_mode_id;
452 uint8_t refreshrate;
491 uint8_t mem_module_id;
492 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
493 uint8_t reserved1[2];
530 uint8_t mem_module_id;
531 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
532 uint8_t reserved1[2];
535 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
536 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
537 uint8_t board_i2c_feature_slave_addr;
538 uint8_t reserved3;
558 uint8_t mem_module_id;
559 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
560 uint8_t reserved1[2];
563 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
564 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
565 uint8_t board_i2c_feature_slave_addr;
566 uint8_t reserved3;
586 uint8_t mem_module_id;
587 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
588 uint8_t reserved1[2];
591 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
592 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
593 uint8_t board_i2c_feature_slave_addr;
594 uint8_t ras_rom_i2c_slave_addr;
629 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
630 uint8_t pwr_on_de_to_vary_bl;
631 uint8_t pwr_down_vary_bloff_to_de;
632 uint8_t pwr_down_de_to_digoff;
633 uint8_t pwr_off_delay;
634 uint8_t pwr_on_vary_bl_to_blon;
635 uint8_t pwr_down_bloff_to_vary_bloff;
636 uint8_t panel_bpc;
637 uint8_t dpcd_edp_config_cap;
638 uint8_t dpcd_max_link_rate;
639 uint8_t dpcd_max_lane_count;
640 uint8_t dpcd_max_downspread;
641 uint8_t min_allowed_bl_level;
642 uint8_t max_allowed_bl_level;
643 uint8_t bootup_bl_level;
644 uint8_t dplvdsrxid;
671 uint8_t gpio_bitshift;
672 uint8_t gpio_mask_bitshift;
673 uint8_t gpio_id;
674 uint8_t reserved;
793 uint8_t record_type; //An emun to indicate the record type
794 uint8_t record_size; //The size of the whole record in byte
800 uint8_t i2c_id;
801 …uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached …
807 …uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info …
808 uint8_t plugin_pin_state;
860 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
861 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
867 uint8_t flag; // Future expnadibility
868 uint8_t number_of_pins; // Number of GPIO pins used to control the object
906 uint8_t hpd_pin_map[8];
912 uint8_t aux_ddc_map[8];
919 uint8_t maxtmdsclkrate_in2_5mhz;
920 uint8_t reserved;
926 uint8_t connector_type;
927 uint8_t position;
943 uint8_t bracketlen;
944 uint8_t bracketwidth;
945 uint8_t conn_num;
946 uint8_t reserved;
952 uint8_t bracketlen; //Bracket Length in mm
953 uint8_t bracketwidth; //Bracket Width in mm
954 uint8_t conn_num; //Connector numbering
955 uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini)
956 uint8_t reserved1;
957 uint8_t reserved2;
986 uint8_t priority_id;
987 uint8_t reserved;
1007 uint8_t number_of_path;
1008 uint8_t reserved;
1015 uint8_t number_of_path;
1016 uint8_t reserved;
1040 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1041 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1042 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1043 uint8_t ss_reserved;
1044 …uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable wh…
1045 uint8_t reserved1[3];
1048 uint8_t dceip_min_ver;
1049 uint8_t dceip_max_ver;
1050 uint8_t max_disp_pipe_num;
1051 uint8_t max_vbios_active_disp_pipe_num;
1052 uint8_t max_ppll_num;
1053 uint8_t max_disp_phy_num;
1054 uint8_t max_aux_pairs;
1055 uint8_t remotedisplayconfig;
1056 uint8_t reserved3[8];
1072 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1073 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1074 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1075 uint8_t ss_reserved;
1076 …uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable …
1077 …uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingT…
1078 …uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable …
1079 …uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable …
1082 uint8_t dcnip_min_ver;
1083 uint8_t dcnip_max_ver;
1084 uint8_t max_disp_pipe_num;
1085 uint8_t max_vbios_active_disp_pipe_num;
1086 uint8_t max_ppll_num;
1087 uint8_t max_disp_phy_num;
1088 uint8_t max_aux_pairs;
1089 uint8_t remotedisplayconfig;
1090 uint8_t reserved3[8];
1106 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1107 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1108 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1109 uint8_t ss_reserved;
1110 …uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable …
1111 …uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingT…
1112 …uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable …
1113 …uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable …
1116 uint8_t dcnip_min_ver;
1117 uint8_t dcnip_max_ver;
1118 uint8_t max_disp_pipe_num;
1119 uint8_t max_vbios_active_disp_pipe_num;
1120 uint8_t max_ppll_num;
1121 uint8_t max_disp_phy_num;
1122 uint8_t max_aux_pairs;
1123 uint8_t remotedisplayconfig;
1124 uint8_t reserved3[8];
1139 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1140 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1141 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1142 uint8_t ss_reserved;
1143 …uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable wh…
1144 …uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTa…
1145 …uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable wh…
1146 …uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable w…
1149 uint8_t dcnip_min_ver;
1150 uint8_t dcnip_max_ver;
1151 uint8_t max_disp_pipe_num;
1152 uint8_t max_vbios_active_disp_pipum;
1153 uint8_t max_ppll_num;
1154 uint8_t max_disp_phy_num;
1155 uint8_t max_aux_pairs;
1156 uint8_t remotedisplayconfig;
1206 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1207 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1208 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1209 uint8_t ss_reserved;
1211 uint8_t dfp_hardcode_mode_num;
1213 uint8_t dfp_hardcode_refreshrate;
1215 uint8_t vga_hardcode_mode_num;
1217 uint8_t vga_hardcode_refreshrate;
1220 uint8_t dcnip_min_ver;
1221 uint8_t dcnip_max_ver;
1222 uint8_t max_disp_pipe_num;
1223 uint8_t max_vbios_active_disp_pipe_num;
1224 uint8_t max_ppll_num;
1225 uint8_t max_disp_phy_num;
1226 uint8_t max_aux_pairs;
1227 uint8_t remotedisplayconfig;
1260 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
1261 uint8_t hpdlut_index; //An index into external HPD pin LUT
1263 …uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapp…
1264 …uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not inv…
1282 …uint8_t guid[16]; // a GUID is a 16 byte long st…
1284 …uint8_t checksum; // a simple Checksum of the su…
1285 uint8_t stereopinid; // use for eDP panel
1286 uint8_t remotedisplayconfig;
1287 uint8_t edptolvdsrxid;
1288 …uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate …
1289 uint8_t reserved[3]; // for potential expansion
1300 uint8_t profile_id; // SENSOR_PROFILES
1311 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
1312 uint8_t module_name[8];
1318 uint8_t flashlight_id; // 0: Rear, 1: Front
1319 uint8_t name[8];
1335 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1336 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1338 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1339 …uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_e…
1340 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1341 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1345 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1347 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1348 …uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_e…
1352 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1353 uint8_t version;
1368 uint8_t sym_clk;
1369 uint8_t dig_mode;
1370 uint8_t phy_sel;
1372 uint8_t common_seldeemph60__deemph_6db_4_val;
1373 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1374 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1375 uint8_t margin_deemph_lane0__deemph_sel_val;
1381 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1382 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1383 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1384 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1385 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1386 uint8_t reserved1;
1387 …uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1388 uint8_t reserved2;
1392 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1393 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1394 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1395 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1396 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1400 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1401 uint8_t version;
1408 uint8_t ucI2cRegIndex;
1409 uint8_t ucI2cRegVal;
1413 uint8_t HdmiSlvAddr;
1414 uint8_t HdmiRegNum;
1415 uint8_t Hdmi6GRegNum;
1438 …uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type …
1439 uint8_t umachannelnumber; // number of memory channels
1440 …uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1441 uint8_t pwr_on_de_to_vary_bl;
1442 uint8_t pwr_down_vary_bloff_to_de;
1443 uint8_t pwr_down_de_to_digoff;
1444 uint8_t pwr_off_delay;
1445 uint8_t pwr_on_vary_bl_to_blon;
1446 uint8_t pwr_down_bloff_to_vary_bloff;
1447 uint8_t min_allowed_bl_level;
1448 uint8_t htc_hyst_limit;
1449 uint8_t htc_tmp_limit;
1450 uint8_t reserved1;
1451 uint8_t reserved2;
1487 …uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type …
1488 uint8_t umachannelnumber; // number of memory channels
1489 …uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms //
1490 uint8_t pwr_on_de_to_vary_bl;
1491 uint8_t pwr_down_vary_bloff_to_de;
1492 uint8_t pwr_down_de_to_digoff;
1493 uint8_t pwr_off_delay;
1494 uint8_t pwr_on_vary_bl_to_blon;
1495 uint8_t pwr_down_bloff_to_vary_bloff;
1496 uint8_t min_allowed_bl_level;
1497 uint8_t htc_hyst_limit;
1498 uint8_t htc_tmp_limit;
1499 uint8_t reserved1;
1500 uint8_t reserved2;
1526 uint8_t edp_pwr_on_off_delay;
1527 uint8_t edp_pwr_on_vary_bl_to_blon;
1528 uint8_t edp_pwr_down_bloff_to_vary_bloff;
1529 uint8_t edp_panel_bpc;
1530 uint8_t edp_bootup_bl_level;
1531 uint8_t reserved3[3];
1545 …uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type …
1546 uint8_t umachannelnumber; // number of memory channels
1547 uint8_t htc_hyst_limit;
1548 uint8_t htc_tmp_limit;
1549 uint8_t reserved1;
1550 uint8_t reserved2;
1576 uint8_t display_signal_type;
1577 uint8_t phy_sel;
1578 uint8_t preset_level;
1579 uint8_t reserved1;
1582 uint8_t tx_vboost_level;
1583 uint8_t tx_vreg_v2i;
1584 uint8_t tx_vregdrv_byp;
1585 uint8_t tx_term_cntl;
1586 uint8_t tx_peak_level;
1587 uint8_t tx_slew_en;
1588 uint8_t tx_eq_pre;
1589 uint8_t tx_eq_main;
1590 uint8_t tx_eq_post;
1591 uint8_t tx_en_inv_pre;
1592 uint8_t tx_en_inv_post;
1593 uint8_t reserved3;
1614 …uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type …
1615 uint8_t umachannelnumber; // number of memory channels
1616 uint8_t htc_hyst_limit;
1617 uint8_t htc_tmp_limit;
1618 uint8_t reserved1;
1619 uint8_t reserved2;
1711 uint8_t gfxip_min_ver;
1712 uint8_t gfxip_max_ver;
1713 uint8_t max_shader_engines;
1714 uint8_t max_tile_pipes;
1715 uint8_t max_cu_per_sh;
1716 uint8_t max_sh_per_se;
1717 uint8_t max_backends_per_se;
1718 uint8_t max_texture_channel_caches;
1731 uint8_t gfxip_min_ver;
1732 uint8_t gfxip_max_ver;
1733 uint8_t max_shader_engines;
1734 uint8_t max_tile_pipes;
1735 uint8_t max_cu_per_sh;
1736 uint8_t max_sh_per_se;
1737 uint8_t max_backends_per_se;
1738 uint8_t max_texture_channel_caches;
1747 uint8_t active_cu_per_sh;
1748 uint8_t active_rb_per_se;
1756 uint8_t gfxip_min_ver;
1757 uint8_t gfxip_max_ver;
1758 uint8_t max_shader_engines;
1759 uint8_t reserved;
1760 uint8_t max_cu_per_sh;
1761 uint8_t max_sh_per_se;
1762 uint8_t max_backends_per_se;
1763 uint8_t max_texture_channel_caches;
1772 uint8_t active_cu_per_sh;
1773 uint8_t active_rb_per_se;
1781 uint8_t gc_num_max_gs_thds;
1782 uint8_t gc_gs_table_depth;
1783 uint8_t gc_double_offchip_lds_buffer;
1784 uint8_t gc_max_scratch_slots_per_cu;
1791 uint8_t gfxip_min_ver;
1792 uint8_t gfxip_max_ver;
1793 uint8_t max_shader_engines;
1794 uint8_t reserved;
1795 uint8_t max_cu_per_sh;
1796 uint8_t max_sh_per_se;
1797 uint8_t max_backends_per_se;
1798 uint8_t max_texture_channel_caches;
1807 uint8_t active_cu_per_sh;
1808 uint8_t active_rb_per_se;
1816 uint8_t gc_num_max_gs_thds;
1817 uint8_t gc_gs_table_depth;
1818 uint8_t gc_double_offchip_lds_buffer;
1819 uint8_t gc_max_scratch_slots_per_cu;
1822 uint8_t cut_cu;
1823 uint8_t active_cu_total;
1824 uint8_t cu_reserved[2];
1826 uint8_t inactive_cu_per_se[8];
1832 uint8_t gfxip_min_ver;
1833 uint8_t gfxip_max_ver;
1834 uint8_t max_shader_engines;
1835 uint8_t max_tile_pipes;
1836 uint8_t max_cu_per_sh;
1837 uint8_t max_sh_per_se;
1838 uint8_t max_backends_per_se;
1839 uint8_t max_texture_channel_caches;
1848 uint8_t active_wgp_per_se;
1849 uint8_t active_rb_per_se;
1850 uint8_t active_se;
1851 uint8_t reserved1;
1856 uint8_t inactive_wgp[16];
1857 uint8_t inactive_rb[16];
1871 uint8_t smuip_min_ver;
1872 uint8_t smuip_max_ver;
1873 uint8_t smu_rsd1;
1874 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1880 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1881 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1882 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1883 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1884 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1885 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1886 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1887 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1892 uint8_t smuip_min_ver;
1893 uint8_t smuip_max_ver;
1894 uint8_t smu_rsd1;
1895 uint8_t gpuclk_ss_mode;
1901 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1902 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1903 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1904 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1905 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1906 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1907 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1908 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1909 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
1910 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1925 uint8_t smuip_min_ver;
1926 uint8_t smuip_max_ver;
1927 uint8_t waflclk_ss_mode;
1928 uint8_t gpuclk_ss_mode;
1934 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1935 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1936 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1937 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1938 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1939 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1940 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1941 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1942 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
1943 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1966 uint8_t smuip_min_ver;
1967 uint8_t smuip_max_ver;
1968 uint8_t waflclk_ss_mode;
1969 uint8_t gpuclk_ss_mode;
1977 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
1978 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
2023 uint8_t smuip_min_ver;
2024 uint8_t smuip_max_ver;
2025 uint8_t waflclk_ss_mode;
2026 uint8_t gpuclk_ss_mode;
2034 uint8_t pcc_gpio_bit;
2035 uint8_t pcc_gpio_polarity;
2089 uint8_t pcc_gpio_bit;
2090 uint8_t pcc_gpio_polarity;
2152 uint8_t liquid1_i2c_address;
2153 uint8_t liquid2_i2c_address;
2154 uint8_t vr_i2c_address;
2155 uint8_t plx_i2c_address;
2157 uint8_t liquid_i2c_linescl;
2158 uint8_t liquid_i2c_linesda;
2159 uint8_t vr_i2c_linescl;
2160 uint8_t vr_i2c_linesda;
2162 uint8_t plx_i2c_linescl;
2163 uint8_t plx_i2c_linesda;
2164 uint8_t vrsensorpresent;
2165 uint8_t liquidsensorpresent;
2170 uint8_t vddgfxvrmapping;
2171 uint8_t vddsocvrmapping;
2172 uint8_t vddmem0vrmapping;
2173 uint8_t vddmem1vrmapping;
2175 uint8_t gfxulvphasesheddingmask;
2176 uint8_t soculvphasesheddingmask;
2177 uint8_t padding8_v[2];
2180 uint8_t gfxoffset;
2181 uint8_t padding_telemetrygfx;
2184 uint8_t socoffset;
2185 uint8_t padding_telemetrysoc;
2188 uint8_t mem0offset;
2189 uint8_t padding_telemetrymem0;
2192 uint8_t mem1offset;
2193 uint8_t padding_telemetrymem1;
2195 uint8_t acdcgpio;
2196 uint8_t acdcpolarity;
2197 uint8_t vr0hotgpio;
2198 uint8_t vr0hotpolarity;
2200 uint8_t vr1hotgpio;
2201 uint8_t vr1hotpolarity;
2202 uint8_t padding1;
2203 uint8_t padding2;
2205 uint8_t ledpin0;
2206 uint8_t ledpin1;
2207 uint8_t ledpin2;
2208 uint8_t padding8_4;
2210 uint8_t pllgfxclkspreadenabled;
2211 uint8_t pllgfxclkspreadpercent;
2214 uint8_t uclkspreadenabled;
2215 uint8_t uclkspreadpercent;
2218 uint8_t socclkspreadenabled;
2219 uint8_t socclkspreadpercent;
2222 uint8_t acggfxclkspreadenabled;
2223 uint8_t acggfxclkspreadpercent;
2226 uint8_t Vr2_I2C_address;
2227 uint8_t padding_vr2[3];
2240 uint8_t liquid1_i2c_address;
2241 uint8_t liquid2_i2c_address;
2242 uint8_t vr_i2c_address;
2243 uint8_t plx_i2c_address;
2245 uint8_t liquid_i2c_linescl;
2246 uint8_t liquid_i2c_linesda;
2247 uint8_t vr_i2c_linescl;
2248 uint8_t vr_i2c_linesda;
2250 uint8_t plx_i2c_linescl;
2251 uint8_t plx_i2c_linesda;
2252 uint8_t vrsensorpresent;
2253 uint8_t liquidsensorpresent;
2258 uint8_t vddgfxvrmapping;
2259 uint8_t vddsocvrmapping;
2260 uint8_t vddmem0vrmapping;
2261 uint8_t vddmem1vrmapping;
2263 uint8_t gfxulvphasesheddingmask;
2264 uint8_t soculvphasesheddingmask;
2265 uint8_t externalsensorpresent;
2266 uint8_t padding8_v;
2269 uint8_t gfxoffset;
2270 uint8_t padding_telemetrygfx;
2273 uint8_t socoffset;
2274 uint8_t padding_telemetrysoc;
2277 uint8_t mem0offset;
2278 uint8_t padding_telemetrymem0;
2281 uint8_t mem1offset;
2282 uint8_t padding_telemetrymem1;
2284 uint8_t acdcgpio;
2285 uint8_t acdcpolarity;
2286 uint8_t vr0hotgpio;
2287 uint8_t vr0hotpolarity;
2289 uint8_t vr1hotgpio;
2290 uint8_t vr1hotpolarity;
2291 uint8_t padding1;
2292 uint8_t padding2;
2294 uint8_t ledpin0;
2295 uint8_t ledpin1;
2296 uint8_t ledpin2;
2297 uint8_t padding8_4;
2299 uint8_t pllgfxclkspreadenabled;
2300 uint8_t pllgfxclkspreadpercent;
2303 uint8_t uclkspreadenabled;
2304 uint8_t uclkspreadpercent;
2307 uint8_t fclkspreadenabled;
2308 uint8_t fclkspreadpercent;
2311 uint8_t fllgfxclkspreadenabled;
2312 uint8_t fllgfxclkspreadpercent;
2336 uint8_t vddgfxvrmapping;
2337 uint8_t vddsocvrmapping;
2338 uint8_t vddmem0vrmapping;
2339 uint8_t vddmem1vrmapping;
2341 uint8_t gfxulvphasesheddingmask;
2342 uint8_t soculvphasesheddingmask;
2343 uint8_t externalsensorpresent;
2344 uint8_t padding8_v;
2347 uint8_t gfxoffset;
2348 uint8_t padding_telemetrygfx;
2351 uint8_t socoffset;
2352 uint8_t padding_telemetrysoc;
2355 uint8_t mem0offset;
2356 uint8_t padding_telemetrymem0;
2359 uint8_t mem1offset;
2360 uint8_t padding_telemetrymem1;
2363 uint8_t acdcgpio;
2364 uint8_t acdcpolarity;
2365 uint8_t vr0hotgpio;
2366 uint8_t vr0hotpolarity;
2368 uint8_t vr1hotgpio;
2369 uint8_t vr1hotpolarity;
2370 uint8_t padding1;
2371 uint8_t padding2;
2374 uint8_t ledpin0;
2375 uint8_t ledpin1;
2376 uint8_t ledpin2;
2377 uint8_t padding8_4;
2380 uint8_t pllgfxclkspreadenabled;
2381 uint8_t pllgfxclkspreadpercent;
2385 uint8_t uclkspreadenabled;
2386 uint8_t uclkspreadpercent;
2390 uint8_t fclkspreadenabled;
2391 uint8_t fclkspreadpercent;
2395 uint8_t fllgfxclkspreadenabled;
2396 uint8_t fllgfxclkspreadpercent;
2442 uint8_t Enabled;
2443 uint8_t Speed;
2444 uint8_t Padding[2];
2446 uint8_t ControllerPort;
2447 uint8_t ControllerName;
2448 uint8_t ThermalThrotter;
2449 uint8_t I2cProtocol;
2463 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2464 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2465 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2466 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2468 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2469 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2470 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2471 uint8_t Padding8_V;
2475 uint8_t GfxOffset; // in Amps
2476 uint8_t Padding_TelemetryGfx;
2478 uint8_t SocOffset; // in Amps
2479 uint8_t Padding_TelemetrySoc;
2482 uint8_t Mem0Offset; // in Amps
2483 uint8_t Padding_TelemetryMem0;
2486 uint8_t Mem1Offset; // in Amps
2487 uint8_t Padding_TelemetryMem1;
2490 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2491 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2492 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2493 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2495 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2496 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2497 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2498 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2501 uint8_t LedPin0; // GPIO number for LedPin[0]
2502 uint8_t LedPin1; // GPIO number for LedPin[1]
2503 uint8_t LedPin2; // GPIO number for LedPin[2]
2504 uint8_t padding8_4;
2507 uint8_t PllGfxclkSpreadEnabled; // on or off
2508 uint8_t PllGfxclkSpreadPercent; // Q4.4
2512 uint8_t DfllGfxclkSpreadEnabled; // on or off
2513 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2517 uint8_t UclkSpreadEnabled; // on or off
2518 uint8_t UclkSpreadPercent; // Q4.4
2522 uint8_t SoclkSpreadEnabled; // on or off
2523 uint8_t SocclkSpreadPercent; // Q4.4
2546 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields
2547 uint8_t vddsocvrmapping; // use vr_mapping* bitfields
2548 uint8_t vddmemvrmapping; // use vr_mapping* bitfields
2549 uint8_t boardvrmapping; // use vr_mapping* bitfields
2551 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
2552 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in)
2553 uint8_t padding8_v[2];
2557 uint8_t gfxoffset; // in amps
2558 uint8_t padding_telemetrygfx;
2561 uint8_t socoffset; // in amps
2562 uint8_t padding_telemetrysoc;
2565 uint8_t memoffset; // in amps
2566 uint8_t padding_telemetrymem;
2569 uint8_t boardoffset; // in amps
2570 uint8_t padding_telemetryboardinput;
2573 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event
2574 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event
2575 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event
2576 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event
2579 uint8_t pllgfxclkspreadenabled; // on or off
2580 uint8_t pllgfxclkspreadpercent; // q4.4
2584 uint8_t uclkspreadenabled; // on or off
2585 uint8_t uclkspreadpercent; // q4.4
2589 uint8_t fclkspreadenabled; // on or off
2590 uint8_t fclkspreadpercent; // q4.4
2595 uint8_t fllgfxclkspreadenabled; // on or off
2596 uint8_t fllgfxclkspreadpercent; // q4.4
2605 uint8_t drambitwidth; // for dram use only. see dram bit width type defines
2606 uint8_t paddingmem[3];
2613 uint8_t xgmilinkspeed[4];
2614 uint8_t xgmilinkwidth[4];
2634 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2635 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2636 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2637 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2639 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2640 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2641 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2642 uint8_t Padding8_V;
2646 uint8_t GfxOffset; // in Amps
2647 uint8_t Padding_TelemetryGfx;
2649 uint8_t SocOffset; // in Amps
2650 uint8_t Padding_TelemetrySoc;
2653 uint8_t Mem0Offset; // in Amps
2654 uint8_t Padding_TelemetryMem0;
2657 uint8_t Mem1Offset; // in Amps
2658 uint8_t Padding_TelemetryMem1;
2661 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2662 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2663 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2664 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2666 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2667 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2668 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2669 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2672 uint8_t LedPin0; // GPIO number for LedPin[0]
2673 uint8_t LedPin1; // GPIO number for LedPin[1]
2674 uint8_t LedPin2; // GPIO number for LedPin[2]
2675 uint8_t padding8_4;
2678 uint8_t PllGfxclkSpreadEnabled; // on or off
2679 uint8_t PllGfxclkSpreadPercent; // Q4.4
2683 uint8_t DfllGfxclkSpreadEnabled; // on or off
2684 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2688 uint8_t UclkSpreadEnabled; // on or off
2689 uint8_t UclkSpreadPercent; // Q4.4
2693 uint8_t SoclkSpreadEnabled; // on or off
2694 uint8_t SocclkSpreadPercent; // Q4.4
2705 uint8_t GpioI2cScl; // Serial Clock
2706 uint8_t GpioI2cSda; // Serial Data
2710 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed
2711 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status
2715 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT]
2717 uint8_t MvddUlvPhaseSheddingMask;
2718 uint8_t VddciUlvPhaseSheddingMask;
2719 uint8_t Padding8_Psi1;
2720 uint8_t Padding8_Psi2;
2727 uint8_t Enabled;
2728 uint8_t Speed;
2729 uint8_t SlaveAddress;
2730 uint8_t ControllerPort;
2731 uint8_t ControllerName;
2732 uint8_t ThermalThrotter;
2733 uint8_t I2cProtocol;
2734 uint8_t PaddingConfig;
2747 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1
2748 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1
2749 …uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when enter…
2750 uint8_t I2cSpare;
2753 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2754 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2755 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2756 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2758 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2759 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2760 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2761 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2765 uint8_t GfxOffset; // in Amps
2766 uint8_t Padding_TelemetryGfx;
2769 uint8_t SocOffset; // in Amps
2770 uint8_t Padding_TelemetrySoc;
2773 uint8_t Mem0Offset; // in Amps
2774 uint8_t Padding_TelemetryMem0;
2777 uint8_t Mem1Offset; // in Amps
2778 uint8_t Padding_TelemetryMem1;
2783 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2784 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2785 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2786 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2788 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2789 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2790 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2791 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2794 uint8_t LedPin0; // GPIO number for LedPin[0]
2795 uint8_t LedPin1; // GPIO number for LedPin[1]
2796 uint8_t LedPin2; // GPIO number for LedPin[2]
2797 uint8_t LedEnableMask;
2799 uint8_t LedPcie; // GPIO number for PCIE results
2800 uint8_t LedError; // GPIO number for Error Cases
2801 uint8_t LedSpare1[2];
2806 uint8_t PllGfxclkSpreadEnabled; // on or off
2807 uint8_t PllGfxclkSpreadPercent; // Q4.4
2811 uint8_t DfllGfxclkSpreadEnabled; // on or off
2812 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2816 uint8_t UclkSpreadEnabled; // on or off
2817 uint8_t UclkSpreadPercent; // Q4.4
2821 uint8_t FclkSpreadEnabled; // on or off
2822 uint8_t FclkSpreadPercent; // Q4.4
2828 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
2829 uint8_t PaddingMem1[3];
2836 uint8_t XgmiLinkSpeed [4];
2837 uint8_t XgmiLinkWidth [4];
2855 uint8_t GfxOffset; // in Amps
2856 uint8_t Padding_TelemetryGfx;
2859 uint8_t SocOffset; // in Amps
2860 uint8_t Padding_TelemetrySoc;
2863 uint8_t MemOffset; // in Amps
2864 uint8_t Padding_TelemetryMem;
2867 uint8_t BoardOffset; // in Amps
2868 uint8_t Padding_TelemetryBoardInput;
2875 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2876 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2877 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2878 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2881 uint8_t UclkSpreadEnabled; // on or off
2882 uint8_t UclkSpreadPercent; // Q4.4
2886 uint8_t FclkSpreadEnabled; // on or off
2887 uint8_t FclkSpreadPercent; // Q4.4
2894 uint8_t GpioI2cScl; // Serial Clock
2895 uint8_t GpioI2cSda; // Serial Data
2930 uint8_t enable_gb_vdroop_table_cksoff;
2931 uint8_t enable_gb_vdroop_table_ckson;
2932 uint8_t enable_gb_fuse_table_cksoff;
2933 uint8_t enable_gb_fuse_table_ckson;
2935 uint8_t enable_apply_avfs_cksoff_voltage;
2936 uint8_t reserved;
2974 uint8_t enable_gb_vdroop_table_cksoff;
2975 uint8_t enable_gb_vdroop_table_ckson;
2976 uint8_t enable_gb_fuse_table_cksoff;
2977 uint8_t enable_gb_fuse_table_ckson;
2979 uint8_t enable_apply_avfs_cksoff_voltage;
2980 uint8_t reserved;
2999 uint8_t enable_acg_gb_vdroop_table;
3000 uint8_t enable_acg_gb_fuse_table;
3023 uint8_t uvdip_min_ver;
3024 uint8_t uvdip_max_ver;
3025 uint8_t vceip_min_ver;
3026 uint8_t vceip_max_ver;
3051 uint8_t umcip_min_ver;
3052 uint8_t umcip_max_ver;
3053 uint8_t vram_type; //enum of atom_dgpu_vram_type
3054 uint8_t umc_config;
3078 uint8_t umcip_min_ver;
3079 uint8_t umcip_max_ver;
3080 uint8_t vram_type; //enum of atom_dgpu_vram_type
3081 uint8_t umc_config;
3098 uint8_t umcip_min_ver;
3099 uint8_t umcip_max_ver;
3100 uint8_t vram_type; //enum of atom_dgpu_vram_type
3101 uint8_t umc_config;
3123 uint8_t umcip_min_ver;
3124 uint8_t umcip_max_ver;
3125 uint8_t vram_type;
3126 uint8_t umc_config;
3132 uint8_t channel_num;
3133 uint8_t channel_width;
3134 uint8_t channel_reserve[2];
3135 uint8_t umc_info_reserved[16];
3151 uint8_t ext_memory_id; // Current memory module ID
3152 uint8_t memory_type; // enum of atom_dgpu_vram_type
3153 uint8_t channel_num; // Number of mem. channels supported in this module
3154 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3155 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3156 uint8_t tunningset_id; // MC phy registers set per.
3157 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3158 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3159 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id
3160 uint8_t vram_rsd2; // reserved
3174 uint8_t vram_module_num; // indicate number of VRAM module
3175 uint8_t umcip_min_ver;
3176 uint8_t umcip_max_ver;
3177 …uint8_t mc_phy_tile_num; // indicate the MCD tile number which use i…
3187 uint8_t density;
3188 uint8_t tunningset_id;
3189 uint8_t ext_memory_id;
3190 uint8_t dram_vendor_id;
3209 uint8_t vram_module_num;
3210 uint8_t umcip_min_ver;
3211 uint8_t umcip_max_ver;
3212 uint8_t mc_phy_tile_num;
3213 uint8_t memory_type;
3214 uint8_t channel_num;
3215 uint8_t channel_width;
3216 uint8_t reserved1;
3274 uint8_t ext_memory_id; // Current memory module ID
3275 uint8_t memory_type; // enum of atom_dgpu_vram_type
3276 uint8_t channel_num; // Number of mem. channels supported in this module
3277 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3278 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3279 uint8_t tunningset_id; // MC phy registers set per
3280 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3281 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3282 uint8_t vram_flags; // bit0= bankgroup enable
3283 uint8_t vram_rsd2; // reserved
3301 uint8_t vram_module_num; // indicate number of VRAM module
3302 uint8_t umcip_min_ver;
3303 uint8_t umcip_max_ver;
3304 …uint8_t mc_phy_tile_num; // indicate the MCD tile number which use i…
3314 uint8_t ext_memory_id; // Current memory module ID
3315 uint8_t memory_type; // enum of atom_dgpu_vram_type
3316 uint8_t channel_num; // Number of mem. channels supported in this module
3317 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3318 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3319 uint8_t tunningset_id; // MC phy registers set per.
3321 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3322 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3323 uint8_t vram_flags; // bit0= bankgroup enable
3324 uint8_t vram_rsd2; // reserved
3337 uint8_t RL;
3338 uint8_t WL;
3339 uint8_t tRAS;
3340 uint8_t tRC;
3343 uint8_t tRFC;
3344 uint8_t tRFCpb;
3346 uint8_t tRREFD;
3347 uint8_t tRCDRD;
3348 uint8_t tRCDWR;
3349 uint8_t tRP;
3351 uint8_t tRRDS;
3352 uint8_t tRRDL;
3353 uint8_t tWR;
3354 uint8_t tWTRS;
3356 uint8_t tWTRL;
3357 uint8_t tFAW;
3358 uint8_t tCCDS;
3359 uint8_t tCCDL;
3361 uint8_t tCRCRL;
3362 uint8_t tCRCWL;
3363 uint8_t tCKE;
3364 uint8_t tCKSRE;
3366 uint8_t tCKSRX;
3367 uint8_t tRTPS;
3368 uint8_t tRTPL;
3369 uint8_t tMRD;
3371 uint8_t tMOD;
3372 uint8_t tXS;
3373 uint8_t tXHP;
3374 uint8_t tXSMRS;
3378 uint8_t tPD;
3379 uint8_t tXP;
3380 uint8_t tCPDED;
3381 uint8_t tACTPDE;
3383 uint8_t tPREPDE;
3384 uint8_t tREFPDE;
3385 uint8_t tMRSPDEN;
3386 uint8_t tRDSRE;
3388 uint8_t tWRSRE;
3389 uint8_t tPPD;
3390 uint8_t tCCDMW;
3391 uint8_t tWTRTR;
3393 uint8_t tLTLTR;
3394 uint8_t tREFTR;
3395 uint8_t VNDR;
3396 uint8_t reserved[9];
3411 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK
3425 uint8_t vram_module_num; // indicate number of VRAM module
3426 uint8_t umcip_min_ver;
3427 uint8_t umcip_max_ver;
3428 …uint8_t mc_phy_tile_num; // indicate the MCD tile number which use i…
3442 uint8_t vram_module_num;
3443 uint8_t umcip_min_ver;
3444 uint8_t umcip_max_ver;
3445 uint8_t mc_phy_tile_num;
3460 uint8_t voltage_type; //enum atom_voltage_type
3461 uint8_t voltage_mode; //enum atom_voltage_object_mode
3479 uint8_t regulator_id; //Indicate Voltage Regulator Id
3480 uint8_t i2c_id;
3481 uint8_t i2c_slave_addr;
3482 uint8_t i2c_control_offset;
3483 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
3484 …uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in un…
3485 uint8_t reserved[2];
3506 …uint8_t gpio_control_id; // default is 0 which indicate control through CG VI…
3507 …uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value L…
3508 uint8_t phase_delay_us; // phase delay in unit of micro second
3509 uint8_t reserved;
3517 …uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and…
3518 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
3519 uint8_t psi0_enable; //
3520 uint8_t maxvstep;
3521 uint8_t telemetry_offset;
3522 uint8_t telemetry_gain;
3529 uint8_t merged_powerrail_type; //enum atom_voltage_type
3530 uint8_t reserved[3];
3675 uint8_t voltagetype; /* enum atom_voltage_type */
3676 …uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_…
3724 uint8_t pll_ss_enable;
3725 uint8_t reserved;
3740 uint8_t reserved;
3741 uint8_t bitslen;
3759 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
3760 …uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLO…
3761 uint8_t command; // enum of atom_get_smu_clock_info_command
3762 …uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid wh…
3940 uint8_t ucode_func_id;
3941 uint8_t ucode_reserved[3];
3956 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
3957 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
3959 uint8_t encoder_mode; // Encoder mode:
3960 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
3961 uint8_t crtc_id; // enum of atom_crtc_def
3962 …uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepc…
3963 uint8_t reserved1[2];
4002 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
4003 …uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK …
4004 …uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when u…
4005 …uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use on…
4049 uint8_t crtc_id; // enum atom_crtc_def
4050 uint8_t blanking; // enum atom_blank_crtc_command
4066 uint8_t crtc_id; // enum atom_crtc_def
4067 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
4068 uint8_t padding[2];
4077 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
4078 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
4079 uint8_t padding[2];
4102 uint8_t h_border;
4103 uint8_t v_border;
4104 uint8_t crtc_id; // enum atom_crtc_def
4105 uint8_t encoder_mode; // atom_encode_mode_def
4106 uint8_t padding[2];
4115 uint8_t i2cspeed_khz;
4117 uint8_t regindex;
4118 uint8_t status; /* enum atom_process_i2c_flag */
4121 uint8_t flag; /* enum atom_process_i2c_status */
4122 uint8_t trans_bytes;
4123 uint8_t slave_addr;
4124 uint8_t i2c_id;
4152 uint8_t channelid;
4154 uint8_t reply_status;
4155 uint8_t aux_delay;
4157 uint8_t dataout_len;
4158 …uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, …
4168 uint8_t crtc_id; // enum atom_crtc_def
4169 uint8_t encoder_id; // enum atom_dig_def
4170 uint8_t encode_mode; // enum atom_encode_mode_def
4171 uint8_t dst_bpc; // enum atom_panel_bit_per_color
4221 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4222 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
4223 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
4224 uint8_t lanenum; // Lane number
4226 uint8_t bitpercolor;
4227 …uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz…
4228 uint8_t reserved[2];
4233 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4234 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
4235 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
4236 uint8_t lanenum; // Lane number
4237 uint8_t symclk_10khz; // Symbol Clock in 10Khz
4238 uint8_t hpd_sel;
4239 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4240 uint8_t reserved[2];
4245 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4246 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
4247 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
4248 uint8_t reserved1;
4254 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4255 uint8_t action; // = rest of generic encoder command which does not carry any parameters
4256 uint8_t reserved1[2];
4275 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
4276 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
4278 uint8_t digmode; // enum atom_encode_mode_def
4279 …uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "D…
4281 uint8_t lanenum; // Lane number 1, 2, 4, 8
4283 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
4284 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4285 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
4286 uint8_t reserved;
4364 …uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENAB…
4365 uint8_t action; //
4366 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
4367 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
4368 …uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPU…
4369 uint8_t hpd_id;
4417 uint8_t revision;
4418 uint8_t checksum;
4419 uint8_t oemId[6];
4420 uint8_t oemTableId[8]; //UINT64 OemTableId;
4428 uint8_t tableUUID[16]; //0x24
4449 uint8_t vbioscontent[1];
4454 uint8_t lib1content[1];