118 #define SRI(reg_name, block, id)\  argument
122 #define SRI2(reg_name, block, id)\  argument
126 #define SRIR(var_name, reg_name, block, id)\  argument
130 #define SRII(reg_name, block, id)\  argument
134 #define SRII2(reg_name_pre, reg_name_post, id)\  argument
139 #define SRII_MPC_RMU(reg_name, block, id)\  argument
143 #define SRII_DWB(reg_name, temp_name, block, id)\  argument
147 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\  argument
150 #define DCCG_SRII(reg_name, block, id)\  argument
154 #define VUPDATE_SRII(reg_name, block, id)\  argument
216 #define abm_regs(id)\  argument
236 #define audio_regs(id)\  argument
264 #define vpg_regs(id)\  argument
284 #define afmt_regs(id)\  argument
304 #define stream_enc_regs(id)\  argument
325 #define aux_regs(id)\  argument
337 #define hpd_regs(id)\  argument
350 #define link_regs(id, phyid)\  argument
383 #define panel_cntl_regs(id)\  argument
401 #define dpp_regs(id)\  argument
421 #define opp_regs(id)\  argument
441 #define aux_engine_regs(id)\  argument
456 #define dwbc_regs_dcn3(id)\  argument
473 #define mcif_wb_regs_dcn3(id)\  argument
490 #define dsc_regsDCN20(id)\  argument
532 #define optc_regs(id)\  argument
551 #define hubp_regs(id)\  argument
606 #define vmid_regs(id)\  argument
760 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }  argument
1250 		enum clock_source_id id,  in dcn301_clock_source_create()