Lines Matching refs:pool
804 static void dce80_resource_destruct(struct dce110_resource_pool *pool) in dce80_resource_destruct() argument
808 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
809 if (pool->base.opps[i] != NULL) in dce80_resource_destruct()
810 dce110_opp_destroy(&pool->base.opps[i]); in dce80_resource_destruct()
812 if (pool->base.transforms[i] != NULL) in dce80_resource_destruct()
813 dce80_transform_destroy(&pool->base.transforms[i]); in dce80_resource_destruct()
815 if (pool->base.ipps[i] != NULL) in dce80_resource_destruct()
816 dce_ipp_destroy(&pool->base.ipps[i]); in dce80_resource_destruct()
818 if (pool->base.mis[i] != NULL) { in dce80_resource_destruct()
819 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce80_resource_destruct()
820 pool->base.mis[i] = NULL; in dce80_resource_destruct()
823 if (pool->base.timing_generators[i] != NULL) { in dce80_resource_destruct()
824 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); in dce80_resource_destruct()
825 pool->base.timing_generators[i] = NULL; in dce80_resource_destruct()
829 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
830 if (pool->base.engines[i] != NULL) in dce80_resource_destruct()
831 dce110_engine_destroy(&pool->base.engines[i]); in dce80_resource_destruct()
832 if (pool->base.hw_i2cs[i] != NULL) { in dce80_resource_destruct()
833 kfree(pool->base.hw_i2cs[i]); in dce80_resource_destruct()
834 pool->base.hw_i2cs[i] = NULL; in dce80_resource_destruct()
836 if (pool->base.sw_i2cs[i] != NULL) { in dce80_resource_destruct()
837 kfree(pool->base.sw_i2cs[i]); in dce80_resource_destruct()
838 pool->base.sw_i2cs[i] = NULL; in dce80_resource_destruct()
842 for (i = 0; i < pool->base.stream_enc_count; i++) { in dce80_resource_destruct()
843 if (pool->base.stream_enc[i] != NULL) in dce80_resource_destruct()
844 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); in dce80_resource_destruct()
847 for (i = 0; i < pool->base.clk_src_count; i++) { in dce80_resource_destruct()
848 if (pool->base.clock_sources[i] != NULL) { in dce80_resource_destruct()
849 dce80_clock_source_destroy(&pool->base.clock_sources[i]); in dce80_resource_destruct()
853 if (pool->base.abm != NULL) in dce80_resource_destruct()
854 dce_abm_destroy(&pool->base.abm); in dce80_resource_destruct()
856 if (pool->base.dmcu != NULL) in dce80_resource_destruct()
857 dce_dmcu_destroy(&pool->base.dmcu); in dce80_resource_destruct()
859 if (pool->base.dp_clock_source != NULL) in dce80_resource_destruct()
860 dce80_clock_source_destroy(&pool->base.dp_clock_source); in dce80_resource_destruct()
862 for (i = 0; i < pool->base.audio_count; i++) { in dce80_resource_destruct()
863 if (pool->base.audios[i] != NULL) { in dce80_resource_destruct()
864 dce_aud_destroy(&pool->base.audios[i]); in dce80_resource_destruct()
868 if (pool->base.irqs != NULL) { in dce80_resource_destruct()
869 dal_irq_service_destroy(&pool->base.irqs); in dce80_resource_destruct()
928 static void dce80_destroy_resource_pool(struct resource_pool **pool) in dce80_destroy_resource_pool() argument
930 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); in dce80_destroy_resource_pool()
934 *pool = NULL; in dce80_destroy_resource_pool()
951 struct dce110_resource_pool *pool) in dce80_construct() argument
959 pool->base.res_cap = &res_cap; in dce80_construct()
960 pool->base.funcs = &dce80_res_pool_funcs; in dce80_construct()
966 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; in dce80_construct()
967 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
968 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
985 pool->base.dp_clock_source = in dce80_construct()
988 pool->base.clock_sources[0] = in dce80_construct()
990 pool->base.clock_sources[1] = in dce80_construct()
992 pool->base.clock_sources[2] = in dce80_construct()
994 pool->base.clk_src_count = 3; in dce80_construct()
997 pool->base.dp_clock_source = in dce80_construct()
1000 pool->base.clock_sources[0] = in dce80_construct()
1002 pool->base.clock_sources[1] = in dce80_construct()
1004 pool->base.clk_src_count = 2; in dce80_construct()
1007 if (pool->base.dp_clock_source == NULL) { in dce80_construct()
1013 for (i = 0; i < pool->base.clk_src_count; i++) { in dce80_construct()
1014 if (pool->base.clock_sources[i] == NULL) { in dce80_construct()
1021 pool->base.dmcu = dce_dmcu_create(ctx, in dce80_construct()
1025 if (pool->base.dmcu == NULL) { in dce80_construct()
1031 pool->base.abm = dce_abm_create(ctx, in dce80_construct()
1035 if (pool->base.abm == NULL) { in dce80_construct()
1044 pool->base.irqs = dal_irq_service_dce80_create(&init_data); in dce80_construct()
1045 if (!pool->base.irqs) in dce80_construct()
1049 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1050 pool->base.timing_generators[i] = dce80_timing_generator_create( in dce80_construct()
1052 if (pool->base.timing_generators[i] == NULL) { in dce80_construct()
1058 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce80_construct()
1059 if (pool->base.mis[i] == NULL) { in dce80_construct()
1065 pool->base.ipps[i] = dce80_ipp_create(ctx, i); in dce80_construct()
1066 if (pool->base.ipps[i] == NULL) { in dce80_construct()
1072 pool->base.transforms[i] = dce80_transform_create(ctx, i); in dce80_construct()
1073 if (pool->base.transforms[i] == NULL) { in dce80_construct()
1079 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce80_construct()
1080 if (pool->base.opps[i] == NULL) { in dce80_construct()
1087 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1088 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce80_construct()
1089 if (pool->base.engines[i] == NULL) { in dce80_construct()
1095 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); in dce80_construct()
1096 if (pool->base.hw_i2cs[i] == NULL) { in dce80_construct()
1102 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); in dce80_construct()
1103 if (pool->base.sw_i2cs[i] == NULL) { in dce80_construct()
1111 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1118 if (!resource_construct(num_virtual_links, dc, &pool->base, in dce80_construct()
1128 dce80_resource_destruct(pool); in dce80_construct()
1136 struct dce110_resource_pool *pool = in dce80_create_resource_pool() local
1139 if (!pool) in dce80_create_resource_pool()
1142 if (dce80_construct(num_virtual_links, dc, pool)) in dce80_create_resource_pool()
1143 return &pool->base; in dce80_create_resource_pool()
1145 kfree(pool); in dce80_create_resource_pool()
1153 struct dce110_resource_pool *pool) in dce81_construct() argument
1161 pool->base.res_cap = &res_cap_81; in dce81_construct()
1162 pool->base.funcs = &dce80_res_pool_funcs; in dce81_construct()
1168 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; in dce81_construct()
1169 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1170 pool->base.timing_generator_count = res_cap_81.num_timing_generator; in dce81_construct()
1185 pool->base.dp_clock_source = in dce81_construct()
1188 pool->base.clock_sources[0] = in dce81_construct()
1190 pool->base.clock_sources[1] = in dce81_construct()
1192 pool->base.clock_sources[2] = in dce81_construct()
1194 pool->base.clk_src_count = 3; in dce81_construct()
1197 pool->base.dp_clock_source = in dce81_construct()
1200 pool->base.clock_sources[0] = in dce81_construct()
1202 pool->base.clock_sources[1] = in dce81_construct()
1204 pool->base.clk_src_count = 2; in dce81_construct()
1207 if (pool->base.dp_clock_source == NULL) { in dce81_construct()
1213 for (i = 0; i < pool->base.clk_src_count; i++) { in dce81_construct()
1214 if (pool->base.clock_sources[i] == NULL) { in dce81_construct()
1221 pool->base.dmcu = dce_dmcu_create(ctx, in dce81_construct()
1225 if (pool->base.dmcu == NULL) { in dce81_construct()
1231 pool->base.abm = dce_abm_create(ctx, in dce81_construct()
1235 if (pool->base.abm == NULL) { in dce81_construct()
1244 pool->base.irqs = dal_irq_service_dce80_create(&init_data); in dce81_construct()
1245 if (!pool->base.irqs) in dce81_construct()
1249 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1250 pool->base.timing_generators[i] = dce80_timing_generator_create( in dce81_construct()
1252 if (pool->base.timing_generators[i] == NULL) { in dce81_construct()
1258 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce81_construct()
1259 if (pool->base.mis[i] == NULL) { in dce81_construct()
1265 pool->base.ipps[i] = dce80_ipp_create(ctx, i); in dce81_construct()
1266 if (pool->base.ipps[i] == NULL) { in dce81_construct()
1272 pool->base.transforms[i] = dce80_transform_create(ctx, i); in dce81_construct()
1273 if (pool->base.transforms[i] == NULL) { in dce81_construct()
1279 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce81_construct()
1280 if (pool->base.opps[i] == NULL) { in dce81_construct()
1287 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1288 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce81_construct()
1289 if (pool->base.engines[i] == NULL) { in dce81_construct()
1295 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); in dce81_construct()
1296 if (pool->base.hw_i2cs[i] == NULL) { in dce81_construct()
1302 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); in dce81_construct()
1303 if (pool->base.sw_i2cs[i] == NULL) { in dce81_construct()
1311 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1318 if (!resource_construct(num_virtual_links, dc, &pool->base, in dce81_construct()
1328 dce80_resource_destruct(pool); in dce81_construct()
1336 struct dce110_resource_pool *pool = in dce81_create_resource_pool() local
1339 if (!pool) in dce81_create_resource_pool()
1342 if (dce81_construct(num_virtual_links, dc, pool)) in dce81_create_resource_pool()
1343 return &pool->base; in dce81_create_resource_pool()
1345 kfree(pool); in dce81_create_resource_pool()
1353 struct dce110_resource_pool *pool) in dce83_construct() argument
1361 pool->base.res_cap = &res_cap_83; in dce83_construct()
1362 pool->base.funcs = &dce80_res_pool_funcs; in dce83_construct()
1368 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; in dce83_construct()
1369 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1370 pool->base.timing_generator_count = res_cap_83.num_timing_generator; in dce83_construct()
1386 pool->base.dp_clock_source = in dce83_construct()
1389 pool->base.clock_sources[0] = in dce83_construct()
1391 pool->base.clock_sources[1] = in dce83_construct()
1393 pool->base.clk_src_count = 2; in dce83_construct()
1396 pool->base.dp_clock_source = in dce83_construct()
1399 pool->base.clock_sources[0] = in dce83_construct()
1401 pool->base.clk_src_count = 1; in dce83_construct()
1404 if (pool->base.dp_clock_source == NULL) { in dce83_construct()
1410 for (i = 0; i < pool->base.clk_src_count; i++) { in dce83_construct()
1411 if (pool->base.clock_sources[i] == NULL) { in dce83_construct()
1418 pool->base.dmcu = dce_dmcu_create(ctx, in dce83_construct()
1422 if (pool->base.dmcu == NULL) { in dce83_construct()
1428 pool->base.abm = dce_abm_create(ctx, in dce83_construct()
1432 if (pool->base.abm == NULL) { in dce83_construct()
1441 pool->base.irqs = dal_irq_service_dce80_create(&init_data); in dce83_construct()
1442 if (!pool->base.irqs) in dce83_construct()
1446 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
1447 pool->base.timing_generators[i] = dce80_timing_generator_create( in dce83_construct()
1449 if (pool->base.timing_generators[i] == NULL) { in dce83_construct()
1455 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce83_construct()
1456 if (pool->base.mis[i] == NULL) { in dce83_construct()
1462 pool->base.ipps[i] = dce80_ipp_create(ctx, i); in dce83_construct()
1463 if (pool->base.ipps[i] == NULL) { in dce83_construct()
1469 pool->base.transforms[i] = dce80_transform_create(ctx, i); in dce83_construct()
1470 if (pool->base.transforms[i] == NULL) { in dce83_construct()
1476 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce83_construct()
1477 if (pool->base.opps[i] == NULL) { in dce83_construct()
1484 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
1485 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce83_construct()
1486 if (pool->base.engines[i] == NULL) { in dce83_construct()
1492 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); in dce83_construct()
1493 if (pool->base.hw_i2cs[i] == NULL) { in dce83_construct()
1499 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); in dce83_construct()
1500 if (pool->base.sw_i2cs[i] == NULL) { in dce83_construct()
1508 dc->caps.max_planes = pool->base.pipe_count; in dce83_construct()
1515 if (!resource_construct(num_virtual_links, dc, &pool->base, in dce83_construct()
1525 dce80_resource_destruct(pool); in dce83_construct()
1533 struct dce110_resource_pool *pool = in dce83_create_resource_pool() local
1536 if (!pool) in dce83_create_resource_pool()
1539 if (dce83_construct(num_virtual_links, dc, pool)) in dce83_create_resource_pool()
1540 return &pool->base; in dce83_create_resource_pool()