178 	union dce_dmcu_psr_config_data_reg2 masterCmdData2;  in dce_dmcu_setup_psr()  local
253 	masterCmdData2.u32All = 0;  in dce_dmcu_setup_psr()
254 	masterCmdData2.bits.dig_fe = psr_context->engineId;  in dce_dmcu_setup_psr()
255 	masterCmdData2.bits.dig_be = psr_context->transmitterId;  in dce_dmcu_setup_psr()
256 	masterCmdData2.bits.skip_wait_for_pll_lock =  in dce_dmcu_setup_psr()
258 	masterCmdData2.bits.frame_delay = psr_context->frame_delay;  in dce_dmcu_setup_psr()
259 	masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;  in dce_dmcu_setup_psr()
260 	masterCmdData2.bits.num_of_controllers =  in dce_dmcu_setup_psr()
263 			masterCmdData2.u32All);  in dce_dmcu_setup_psr()
609 	union dce_dmcu_psr_config_data_reg2 masterCmdData2;  in dcn10_dmcu_setup_psr()  local
692 	masterCmdData2.u32All = 0;  in dcn10_dmcu_setup_psr()
693 	masterCmdData2.bits.dig_fe = psr_context->engineId;  in dcn10_dmcu_setup_psr()
694 	masterCmdData2.bits.dig_be = psr_context->transmitterId;  in dcn10_dmcu_setup_psr()
695 	masterCmdData2.bits.skip_wait_for_pll_lock =  in dcn10_dmcu_setup_psr()
697 	masterCmdData2.bits.frame_delay = psr_context->frame_delay;  in dcn10_dmcu_setup_psr()
698 	masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;  in dcn10_dmcu_setup_psr()
699 	masterCmdData2.bits.num_of_controllers =  in dcn10_dmcu_setup_psr()
702 			masterCmdData2.u32All);  in dcn10_dmcu_setup_psr()