Lines Matching refs:SR
33 SR(MASTER_COMM_CNTL_REG), \
34 SR(MASTER_COMM_CMD_REG), \
35 SR(MASTER_COMM_DATA_REG1)
39 SR(DC_ABM1_HG_SAMPLE_RATE), \
40 SR(DC_ABM1_LS_SAMPLE_RATE), \
41 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
42 SR(DC_ABM1_HG_MISC_CTRL), \
43 SR(DC_ABM1_IPCSC_COEFF_SEL), \
44 SR(BL1_PWM_CURRENT_ABM_LEVEL), \
45 SR(BL1_PWM_TARGET_ABM_LEVEL), \
46 SR(BL1_PWM_USER_LEVEL), \
47 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
48 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
49 SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
50 SR(DC_ABM1_ACE_THRES_12), \
51 SR(BIOS_SCRATCH_2)
71 SR(DC_ABM1_HG_SAMPLE_RATE), \
72 SR(DC_ABM1_LS_SAMPLE_RATE), \
73 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
74 SR(DC_ABM1_HG_MISC_CTRL), \
75 SR(DC_ABM1_IPCSC_COEFF_SEL), \
76 SR(BL1_PWM_CURRENT_ABM_LEVEL), \
77 SR(BL1_PWM_TARGET_ABM_LEVEL), \
78 SR(BL1_PWM_USER_LEVEL), \
79 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
80 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
81 SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
82 SR(DC_ABM1_ACE_THRES_12), \