Lines Matching defs:var
47 var ACK_SQC_STORE = 1 //workaround for suspected SQC store bug causing incorrect stores u… label
48 var SAVE_AFTER_XNACK_ERROR = 1 //workaround for TCP store failure after XNACK error when A… label
49 var SINGLE_STEP_MISSED_WORKAROUND = (ASIC_FAMILY <= CHIP_ALDEBARAN) //workaround for lost MODE.DE… label
54 var SQ_WAVE_STATUS_SPI_PRIO_SHIFT = 1 label
55 var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 label
56 var SQ_WAVE_STATUS_HALT_MASK = 0x2000 label
57 var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT = 0 label
58 var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE = 1 label
59 var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT = 3 label
60 var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE = 29 label
61 var SQ_WAVE_STATUS_ALLOW_REPLAY_MASK = 0x400000 label
62 var SQ_WAVE_STATUS_ECC_ERR_MASK = 0x20000 label
64 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 label
65 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 label
66 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 label
67 var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ p… label
68 var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 label
71 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 6 label
72 var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SHIFT = 12 label
73 var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SIZE = 6 label
75 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 label
78 var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 label
79 var SQ_WAVE_TRAPSTS_EXCP_MASK = 0x1FF label
80 var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 label
81 var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK = 0x80 label
82 var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 label
83 var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 label
84 var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 label
85 var SQ_WAVE_TRAPSTS_HOST_TRAP_MASK = 0x400000 label
86 var SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK = 0x800000 label
87 var SQ_WAVE_TRAPSTS_WAVE_END_MASK = 0x1000000 label
88 var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK = 0x2000000 label
89 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF label
90 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 label
91 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 label
92 var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 label
93 var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 label
94 var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 label
95 var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 label
96 var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000 label
97 var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK = 0x10000000 label
99 var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12 label
100 var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19 label
102 var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME label
103 var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 label
105 var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 label
107 var TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data label
108 var TTMP_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 label
109 var TTMP_DEBUG_TRAP_ENABLED_SHIFT = 23 label
110 var TTMP_DEBUG_TRAP_ENABLED_MASK = 0x800000 label
113 var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes label
114 var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBU… label
115 var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 label
116 var S_SAVE_PC_HI_HT_MASK = 0x01000000 label
117 var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG label
118 var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 label
120 var s_save_spi_init_lo = exec_lo label
121 var s_save_spi_init_hi = exec_hi label
123 var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]} label
124 var s_save_pc_hi = ttmp1 label
125 var s_save_exec_lo = ttmp2 label
126 var s_save_exec_hi = ttmp3 label
127 var s_save_tmp = ttmp14 label
128 var s_save_trapsts = ttmp15 //not really used until the end of the SAVE routine label
129 var s_save_xnack_mask_lo = ttmp6 label
130 var s_save_xnack_mask_hi = ttmp7 label
131 var s_save_buf_rsrc0 = ttmp8 label
132 var s_save_buf_rsrc1 = ttmp9 label
133 var s_save_buf_rsrc2 = ttmp10 label
134 var s_save_buf_rsrc3 = ttmp11 label
135 var s_save_status = ttmp12 label
136 var s_save_mem_offset = ttmp4 label
137 var s_save_alloc_size = s_save_trapsts //conflict label
138 var s_save_m0 = ttmp5 label
139 var s_save_ttmps_lo = s_save_tmp //no conflict label
140 var s_save_ttmps_hi = s_save_trapsts //no conflict label
142 var s_save_ib_sts = ttmp13 label
144 var s_save_ib_sts = ttmp11 label
148 var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE label
149 var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC label
151 var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG label
152 var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 label
154 var s_restore_spi_init_lo = exec_lo label
155 var s_restore_spi_init_hi = exec_hi label
157 var s_restore_mem_offset = ttmp12 label
158 var s_restore_tmp2 = ttmp13 label
159 var s_restore_alloc_size = ttmp3 label
160 var s_restore_tmp = ttmp2 label
161 var s_restore_mem_offset_save = s_restore_tmp //no conflict label
162 var s_restore_accvgpr_offset_save = ttmp7 label
164 var s_restore_m0 = s_restore_alloc_size //no conflict label
166 var s_restore_mode = s_restore_accvgpr_offset_save label
168 var s_restore_pc_lo = ttmp0 label
169 var s_restore_pc_hi = ttmp1 label
170 var s_restore_exec_lo = ttmp4 label
171 var s_restore_exec_hi = ttmp5 label
172 var s_restore_status = ttmp14 label
173 var s_restore_trapsts = ttmp15 label
174 var s_restore_xnack_mask_lo = xnack_mask_lo label
175 var s_restore_xnack_mask_hi = xnack_mask_hi label
176 var s_restore_buf_rsrc0 = ttmp8 label
177 var s_restore_buf_rsrc1 = ttmp9 label
178 var s_restore_buf_rsrc2 = ttmp10 label
179 var s_restore_buf_rsrc3 = ttmp11 label
180 var s_restore_ttmps_lo = s_restore_tmp //no conflict label
181 var s_restore_ttmps_hi = s_restore_alloc_size //no conflict label