436 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)  in vcn_v4_0_mc_resume_dpg_mode()  argument
445 		if (!indirect) {  in vcn_v4_0_mc_resume_dpg_mode()
448 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
451 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
453 				VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
456 				VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
458 				VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
460 				VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
466 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
469 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
473 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
476 	if (!indirect)  in vcn_v4_0_mc_resume_dpg_mode()
478 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
481 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
484 	if (!indirect) {  in vcn_v4_0_mc_resume_dpg_mode()
487 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
490 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
492 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
495 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
497 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
499 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
502 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
507 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
510 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
512 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
514 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
519 			lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
522 			upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
524 			VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
527 			AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
531 		VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
776       int inst_idx, uint8_t indirect)  in vcn_v4_0_disable_clock_gating_dpg_mode()  argument
807 		VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
811 		VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
815 		VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
819 		VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
884 				bool indirect)  in vcn_v4_0_enable_ras()  argument
897 			      tmp, 0, indirect);  in vcn_v4_0_enable_ras()
902 			      tmp, 0, indirect);  in vcn_v4_0_enable_ras()
914 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)  in vcn_v4_0_start_dpg_mode()  argument
929 	if (indirect)  in vcn_v4_0_start_dpg_mode()
933 	vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);  in vcn_v4_0_start_dpg_mode()
939 		VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
943 		VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);  in vcn_v4_0_start_dpg_mode()
955 		VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
959 		0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);  in vcn_v4_0_start_dpg_mode()
966 		 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);  in vcn_v4_0_start_dpg_mode()
973 		 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);  in vcn_v4_0_start_dpg_mode()
979 		 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);  in vcn_v4_0_start_dpg_mode()
981 	vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect);  in vcn_v4_0_start_dpg_mode()
986 		VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
991 		VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
993 	vcn_v4_0_enable_ras(adev, inst_idx, indirect);  in vcn_v4_0_start_dpg_mode()
998 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1001 	if (indirect)  in vcn_v4_0_start_dpg_mode()