52 	if (adev->irq.ih.ring_size) {  in ih_v6_0_init_register_offset()
53 		ih_regs = &adev->irq.ih.ih_regs;  in ih_v6_0_init_register_offset()
128 					  struct amdgpu_ih_ring *ih,  in ih_v6_0_toggle_ring_interrupts()  argument
134 	ih_regs = &ih->ih_regs;  in ih_v6_0_toggle_ring_interrupts()
139 	if (ih == &adev->irq.ih)  in ih_v6_0_toggle_ring_interrupts()
150 		ih->enabled = true;  in ih_v6_0_toggle_ring_interrupts()
155 		ih->enabled = false;  in ih_v6_0_toggle_ring_interrupts()
156 		ih->rptr = 0;  in ih_v6_0_toggle_ring_interrupts()
172 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};  in ih_v6_0_toggle_interrupts()  local
176 	for (i = 0; i < ARRAY_SIZE(ih); i++) {  in ih_v6_0_toggle_interrupts()
177 		if (ih[i]->ring_size) {  in ih_v6_0_toggle_interrupts()
178 			r = ih_v6_0_toggle_ring_interrupts(adev, ih[i], enable);  in ih_v6_0_toggle_interrupts()
187 static uint32_t ih_v6_0_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)  in ih_v6_0_rb_cntl()  argument
189 	int rb_bufsz = order_base_2(ih->ring_size / 4);  in ih_v6_0_rb_cntl()
192 				   MC_SPACE, ih->use_bus_addr ? 2 : 4);  in ih_v6_0_rb_cntl()
210 static uint32_t ih_v6_0_doorbell_rptr(struct amdgpu_ih_ring *ih)  in ih_v6_0_doorbell_rptr()  argument
214 	if (ih->use_doorbell) {  in ih_v6_0_doorbell_rptr()
217 						 ih->doorbell_index);  in ih_v6_0_doorbell_rptr()
238 				      struct amdgpu_ih_ring *ih)  in ih_v6_0_enable_ring()  argument
243 	ih_regs = &ih->ih_regs;  in ih_v6_0_enable_ring()
246 	WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);  in ih_v6_0_enable_ring()
247 	WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);  in ih_v6_0_enable_ring()
250 	tmp = ih_v6_0_rb_cntl(ih, tmp);  in ih_v6_0_enable_ring()
251 	if (ih == &adev->irq.ih)  in ih_v6_0_enable_ring()
253 	if (ih == &adev->irq.ih1) {  in ih_v6_0_enable_ring()
267 	if (ih == &adev->irq.ih) {  in ih_v6_0_enable_ring()
269 		WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));  in ih_v6_0_enable_ring()
270 		WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);  in ih_v6_0_enable_ring()
277 	WREG32(ih_regs->ih_doorbell_rptr, ih_v6_0_doorbell_rptr(ih));  in ih_v6_0_enable_ring()
295 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};  in ih_v6_0_irq_init()  local
310 		if (ih[0]->use_bus_addr) {  in ih_v6_0_irq_init()
318 	for (i = 0; i < ARRAY_SIZE(ih); i++) {  in ih_v6_0_irq_init()
319 		if (ih[i]->ring_size) {  in ih_v6_0_irq_init()
320 			ret = ih_v6_0_enable_ring(adev, ih[i]);  in ih_v6_0_irq_init()
327 	adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,  in ih_v6_0_irq_init()
328 					    ih[0]->doorbell_index);  in ih_v6_0_irq_init()
392 			      struct amdgpu_ih_ring *ih)  in ih_v6_0_get_wptr()  argument
397 	wptr = le32_to_cpu(*ih->wptr_cpu);  in ih_v6_0_get_wptr()
398 	ih_regs = &ih->ih_regs;  in ih_v6_0_get_wptr()
412 	tmp = (wptr + 32) & ih->ptr_mask;  in ih_v6_0_get_wptr()
415 		 wptr, ih->rptr, tmp);  in ih_v6_0_get_wptr()
416 	ih->rptr = tmp;  in ih_v6_0_get_wptr()
428 	return (wptr & ih->ptr_mask);  in ih_v6_0_get_wptr()
439 			       struct amdgpu_ih_ring *ih)  in ih_v6_0_irq_rearm()  argument
445 	ih_regs = &ih->ih_regs;  in ih_v6_0_irq_rearm()
450 		if ((v < ih->ring_size) && (v != ih->rptr))  in ih_v6_0_irq_rearm()
451 			WDOORBELL32(ih->doorbell_index, ih->rptr);  in ih_v6_0_irq_rearm()
466 			       struct amdgpu_ih_ring *ih)  in ih_v6_0_set_rptr()  argument
470 	if (ih->use_doorbell) {  in ih_v6_0_set_rptr()
472 		*ih->rptr_cpu = ih->rptr;  in ih_v6_0_set_rptr()
473 		WDOORBELL32(ih->doorbell_index, ih->rptr);  in ih_v6_0_set_rptr()
476 			ih_v6_0_irq_rearm(adev, ih);  in ih_v6_0_set_rptr()
478 		ih_regs = &ih->ih_regs;  in ih_v6_0_set_rptr()
479 		WREG32(ih_regs->ih_rb_rptr, ih->rptr);  in ih_v6_0_set_rptr()
545 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);  in ih_v6_0_sw_init()
549 	adev->irq.ih.use_doorbell = true;  in ih_v6_0_sw_init()
550 	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;  in ih_v6_0_sw_init()