156 	uint32_t tmp;  in gfxhub_v1_0_init_tlb_regs()  local
159 	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v1_0_init_tlb_regs()
161 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gfxhub_v1_0_init_tlb_regs()
162 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gfxhub_v1_0_init_tlb_regs()
163 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
165 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
167 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
169 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);  in gfxhub_v1_0_init_tlb_regs()
171 	WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v1_0_init_tlb_regs()
176 	uint32_t tmp;  in gfxhub_v1_0_init_cache_regs()  local
179 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);  in gfxhub_v1_0_init_cache_regs()
180 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gfxhub_v1_0_init_cache_regs()
181 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);  in gfxhub_v1_0_init_cache_regs()
183 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,  in gfxhub_v1_0_init_cache_regs()
185 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);  in gfxhub_v1_0_init_cache_regs()
186 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gfxhub_v1_0_init_cache_regs()
187 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);  in gfxhub_v1_0_init_cache_regs()
188 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);  in gfxhub_v1_0_init_cache_regs()
190 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);  in gfxhub_v1_0_init_cache_regs()
191 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gfxhub_v1_0_init_cache_regs()
192 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gfxhub_v1_0_init_cache_regs()
193 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);  in gfxhub_v1_0_init_cache_regs()
195 	tmp = mmVM_L2_CNTL3_DEFAULT;  in gfxhub_v1_0_init_cache_regs()
197 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);  in gfxhub_v1_0_init_cache_regs()
198 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,  in gfxhub_v1_0_init_cache_regs()
201 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);  in gfxhub_v1_0_init_cache_regs()
202 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,  in gfxhub_v1_0_init_cache_regs()
205 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);  in gfxhub_v1_0_init_cache_regs()
207 	tmp = mmVM_L2_CNTL4_DEFAULT;  in gfxhub_v1_0_init_cache_regs()
209 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);  in gfxhub_v1_0_init_cache_regs()
210 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);  in gfxhub_v1_0_init_cache_regs()
212 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);  in gfxhub_v1_0_init_cache_regs()
213 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);  in gfxhub_v1_0_init_cache_regs()
215 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);  in gfxhub_v1_0_init_cache_regs()
220 	uint32_t tmp;  in gfxhub_v1_0_enable_system_domain()  local
222 	tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);  in gfxhub_v1_0_enable_system_domain()
223 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v1_0_enable_system_domain()
224 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,  in gfxhub_v1_0_enable_system_domain()
226 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,  in gfxhub_v1_0_enable_system_domain()
228 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,  in gfxhub_v1_0_enable_system_domain()
230 	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);  in gfxhub_v1_0_enable_system_domain()
254 	uint32_t tmp;  in gfxhub_v1_0_setup_vmid_config()  local
265 		tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);  in gfxhub_v1_0_setup_vmid_config()
266 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v1_0_setup_vmid_config()
267 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,  in gfxhub_v1_0_setup_vmid_config()
269 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
271 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
274 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
276 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
278 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
280 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
282 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
284 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
291 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
296 				    i * hub->ctx_distance, tmp);  in gfxhub_v1_0_setup_vmid_config()
344 	u32 tmp;  in gfxhub_v1_0_gart_disable()  local
357 	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v1_0_gart_disable()
358 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gfxhub_v1_0_gart_disable()
359 	tmp = REG_SET_FIELD(tmp,  in gfxhub_v1_0_gart_disable()
363 	WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v1_0_gart_disable()
379 	u32 tmp;  in gfxhub_v1_0_set_fault_enable_default()  local
381 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);  in gfxhub_v1_0_set_fault_enable_default()
382 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
384 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
386 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
388 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
390 	tmp = REG_SET_FIELD(tmp,  in gfxhub_v1_0_set_fault_enable_default()
394 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
396 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
398 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
400 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
402 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
404 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
407 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
409 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
412 	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);  in gfxhub_v1_0_set_fault_enable_default()