88 	uint32_t        hpd;  member
94 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
99 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
104 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
109 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
114 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
119 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
279 			       enum amdgpu_hpd_id hpd)  in dce_v10_0_hpd_sense()  argument
283 	if (hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_sense()
286 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &  in dce_v10_0_hpd_sense()
302 				      enum amdgpu_hpd_id hpd)  in dce_v10_0_hpd_set_polarity()  argument
305 	bool connected = dce_v10_0_hpd_sense(adev, hpd);  in dce_v10_0_hpd_set_polarity()
307 	if (hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_set_polarity()
310 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_hpd_set_polarity()
315 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_hpd_set_polarity()
337 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_init()
347 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
349 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
353 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
355 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
357 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
364 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
366 		dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_init()
368 			       amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_init()
392 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_fini()
395 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_fini()
397 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_fini()
400 			       amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_fini()
3045 				       unsigned hpd,  in dce_v10_0_set_hpd_irq_state()  argument
3050 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v10_0_set_hpd_irq_state()
3051 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v10_0_set_hpd_irq_state()
3057 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_set_hpd_irq_state()
3059 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_set_hpd_irq_state()
3062 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_set_hpd_irq_state()
3064 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_set_hpd_irq_state()
3198 				  int hpd)  in dce_v10_0_hpd_int_ack()  argument
3202 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v10_0_hpd_int_ack()
3203 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v10_0_hpd_int_ack()
3207 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_hpd_int_ack()
3209 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_hpd_int_ack()
3285 	unsigned hpd;  in dce_v10_0_hpd_irq()  local
3292 	hpd = entry->src_data[0];  in dce_v10_0_hpd_irq()
3293 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v10_0_hpd_irq()
3294 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v10_0_hpd_irq()
3297 		dce_v10_0_hpd_int_ack(adev, hpd);  in dce_v10_0_hpd_irq()
3299 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v10_0_hpd_irq()