Lines Matching refs:control
171 struct amdgpu_ras_eeprom_control *control) in __get_eeprom_i2c_addr() argument
176 if (!control) in __get_eeprom_i2c_addr()
189 control->i2c_address = ((u32) i2c_addr) << 16; in __get_eeprom_i2c_addr()
198 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
202 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
204 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
207 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
212 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
214 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
219 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
221 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
225 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
258 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) in __write_table_header() argument
261 struct amdgpu_device *adev = to_amdgpu_device(control); in __write_table_header()
265 __encode_table_header_to_buf(&control->tbl_hdr, buf); in __write_table_header()
270 control->i2c_address + in __write_table_header()
271 control->ras_header_offset, in __write_table_header()
314 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) in __write_table_ras_info() argument
316 struct amdgpu_device *adev = to_amdgpu_device(control); in __write_table_ras_info()
326 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); in __write_table_ras_info()
331 control->i2c_address + in __write_table_ras_info()
332 control->ras_info_offset, in __write_table_ras_info()
351 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) in __calc_hdr_byte_sum() argument
358 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); in __calc_hdr_byte_sum()
359 pp = (u8 *) &control->tbl_hdr; in __calc_hdr_byte_sum()
367 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) in __calc_ras_info_byte_sum() argument
373 sz = sizeof(control->tbl_rai); in __calc_ras_info_byte_sum()
374 pp = (u8 *) &control->tbl_rai; in __calc_ras_info_byte_sum()
383 struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_correct_header_tag() argument
386 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_correct_header_tag()
398 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_correct_header_tag()
401 res = __write_table_header(control); in amdgpu_ras_eeprom_correct_header_tag()
402 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_correct_header_tag()
414 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_reset_table() argument
416 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_reset_table()
417 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_reset_table()
418 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; in amdgpu_ras_eeprom_reset_table()
423 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_reset_table()
449 csum = __calc_hdr_byte_sum(control); in amdgpu_ras_eeprom_reset_table()
451 csum += __calc_ras_info_byte_sum(control); in amdgpu_ras_eeprom_reset_table()
454 res = __write_table_header(control); in amdgpu_ras_eeprom_reset_table()
456 res = __write_table_ras_info(control); in amdgpu_ras_eeprom_reset_table()
458 control->ras_num_recs = 0; in amdgpu_ras_eeprom_reset_table()
459 control->ras_fri = 0; in amdgpu_ras_eeprom_reset_table()
461 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs); in amdgpu_ras_eeprom_reset_table()
463 control->bad_channel_bitmap = 0; in amdgpu_ras_eeprom_reset_table()
464 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); in amdgpu_ras_eeprom_reset_table()
467 amdgpu_ras_debugfs_set_ret_size(control); in amdgpu_ras_eeprom_reset_table()
469 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_reset_table()
475 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, in __encode_table_record_to_buf() argument
503 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, in __decode_table_record_from_buf() argument
573 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, in __amdgpu_ras_eeprom_write() argument
576 struct amdgpu_device *adev = to_amdgpu_device(control); in __amdgpu_ras_eeprom_write()
584 control->i2c_address + in __amdgpu_ras_eeprom_write()
585 RAS_INDEX_TO_OFFSET(control, fri), in __amdgpu_ras_eeprom_write()
605 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_append_table() argument
609 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); in amdgpu_ras_eeprom_append_table()
622 __encode_table_record_to_buf(control, &record[i], pp); in amdgpu_ras_eeprom_append_table()
625 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { in amdgpu_ras_eeprom_append_table()
626 control->bad_channel_bitmap |= 1 << record[i].mem_channel; in amdgpu_ras_eeprom_append_table()
658 a = control->ras_fri + control->ras_num_recs; in amdgpu_ras_eeprom_append_table()
660 if (b < control->ras_max_record_count) { in amdgpu_ras_eeprom_append_table()
661 res = __amdgpu_ras_eeprom_write(control, buf, a, num); in amdgpu_ras_eeprom_append_table()
662 } else if (a < control->ras_max_record_count) { in amdgpu_ras_eeprom_append_table()
665 g0 = control->ras_max_record_count - a; in amdgpu_ras_eeprom_append_table()
666 g1 = b % control->ras_max_record_count + 1; in amdgpu_ras_eeprom_append_table()
667 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); in amdgpu_ras_eeprom_append_table()
670 res = __amdgpu_ras_eeprom_write(control, in amdgpu_ras_eeprom_append_table()
675 if (g1 > control->ras_fri) in amdgpu_ras_eeprom_append_table()
676 control->ras_fri = g1 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
678 a %= control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
679 b %= control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
683 res = __amdgpu_ras_eeprom_write(control, buf, a, num); in amdgpu_ras_eeprom_append_table()
686 if (b >= control->ras_fri) in amdgpu_ras_eeprom_append_table()
687 control->ras_fri = (b + 1) % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
695 g0 = control->ras_max_record_count - a; in amdgpu_ras_eeprom_append_table()
697 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); in amdgpu_ras_eeprom_append_table()
700 res = __amdgpu_ras_eeprom_write(control, in amdgpu_ras_eeprom_append_table()
705 control->ras_fri = g1 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
708 control->ras_num_recs = 1 + (control->ras_max_record_count + b in amdgpu_ras_eeprom_append_table()
709 - control->ras_fri) in amdgpu_ras_eeprom_append_table()
710 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
717 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_update_header() argument
719 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_update_header()
728 control->ras_num_recs >= ras->bad_page_cnt_threshold) { in amdgpu_ras_eeprom_update_header()
731 control->ras_num_recs, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_update_header()
732 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; in amdgpu_ras_eeprom_update_header()
733 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) { in amdgpu_ras_eeprom_update_header()
734 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; in amdgpu_ras_eeprom_update_header()
735 control->tbl_rai.health_percent = 0; in amdgpu_ras_eeprom_update_header()
739 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_update_header()
740 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + in amdgpu_ras_eeprom_update_header()
742 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
744 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + in amdgpu_ras_eeprom_update_header()
745 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
746 control->tbl_hdr.checksum = 0; in amdgpu_ras_eeprom_update_header()
748 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
749 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); in amdgpu_ras_eeprom_update_header()
752 control->tbl_hdr.tbl_size); in amdgpu_ras_eeprom_update_header()
759 control->i2c_address + in amdgpu_ras_eeprom_update_header()
760 control->ras_record_offset, in amdgpu_ras_eeprom_update_header()
779 control->tbl_hdr.version == RAS_TABLE_VER_V2_1 && in amdgpu_ras_eeprom_update_header()
780 control->ras_num_recs < ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_update_header()
781 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - in amdgpu_ras_eeprom_update_header()
782 control->ras_num_recs) * 100) / in amdgpu_ras_eeprom_update_header()
791 csum += __calc_hdr_byte_sum(control); in amdgpu_ras_eeprom_update_header()
792 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_update_header()
793 csum += __calc_ras_info_byte_sum(control); in amdgpu_ras_eeprom_update_header()
796 control->tbl_hdr.checksum = csum; in amdgpu_ras_eeprom_update_header()
797 res = __write_table_header(control); in amdgpu_ras_eeprom_update_header()
798 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) in amdgpu_ras_eeprom_update_header()
799 res = __write_table_ras_info(control); in amdgpu_ras_eeprom_update_header()
818 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_append() argument
822 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_append()
831 } else if (num > control->ras_max_record_count) { in amdgpu_ras_eeprom_append()
833 num, control->ras_max_record_count); in amdgpu_ras_eeprom_append()
837 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_append()
839 res = amdgpu_ras_eeprom_append_table(control, record, num); in amdgpu_ras_eeprom_append()
841 res = amdgpu_ras_eeprom_update_header(control); in amdgpu_ras_eeprom_append()
843 amdgpu_ras_debugfs_set_ret_size(control); in amdgpu_ras_eeprom_append()
845 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_append()
859 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, in __amdgpu_ras_eeprom_read() argument
862 struct amdgpu_device *adev = to_amdgpu_device(control); in __amdgpu_ras_eeprom_read()
870 control->i2c_address + in __amdgpu_ras_eeprom_read()
871 RAS_INDEX_TO_OFFSET(control, fri), in __amdgpu_ras_eeprom_read()
901 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_read() argument
905 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_read()
917 } else if (num > control->ras_num_recs) { in amdgpu_ras_eeprom_read()
919 num, control->ras_num_recs); in amdgpu_ras_eeprom_read()
947 g0 = control->ras_fri + num - 1; in amdgpu_ras_eeprom_read()
948 g1 = g0 % control->ras_max_record_count; in amdgpu_ras_eeprom_read()
949 if (g0 < control->ras_max_record_count) { in amdgpu_ras_eeprom_read()
953 g0 = control->ras_max_record_count - control->ras_fri; in amdgpu_ras_eeprom_read()
957 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_read()
958 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); in amdgpu_ras_eeprom_read()
962 res = __amdgpu_ras_eeprom_read(control, in amdgpu_ras_eeprom_read()
975 __decode_table_record_from_buf(control, &record[i], pp); in amdgpu_ras_eeprom_read()
978 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { in amdgpu_ras_eeprom_read()
979 control->bad_channel_bitmap |= 1 << record[i].mem_channel; in amdgpu_ras_eeprom_read()
985 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_read()
990 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_max_record_count() argument
992 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_max_record_count()
1004 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_size_read() local
1011 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_size_read()
1015 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); in amdgpu_ras_debugfs_eeprom_size_read()
1052 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_debugfs_table_size() argument
1055 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; in amdgpu_ras_debugfs_table_size()
1058 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_debugfs_set_ret_size() argument
1060 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, in amdgpu_ras_debugfs_set_ret_size()
1065 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); in amdgpu_ras_debugfs_set_ret_size()
1073 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; in amdgpu_ras_debugfs_table_read() local
1078 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_debugfs_table_read()
1100 control->tbl_hdr.header, in amdgpu_ras_debugfs_table_read()
1101 control->tbl_hdr.version, in amdgpu_ras_debugfs_table_read()
1102 control->tbl_hdr.first_rec_offset, in amdgpu_ras_debugfs_table_read()
1103 control->tbl_hdr.tbl_size, in amdgpu_ras_debugfs_table_read()
1104 control->tbl_hdr.checksum); in amdgpu_ras_debugfs_table_read()
1130 data_len = amdgpu_ras_debugfs_table_size(control); in amdgpu_ras_debugfs_table_read()
1146 for ( ; size > 0 && s < control->ras_num_recs; s++) { in amdgpu_ras_debugfs_table_read()
1147 u32 ai = RAS_RI_TO_AI(control, s); in amdgpu_ras_debugfs_table_read()
1150 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); in amdgpu_ras_debugfs_table_read()
1153 __decode_table_record_from_buf(control, &record, dare); in amdgpu_ras_debugfs_table_read()
1156 RAS_INDEX_TO_OFFSET(control, ai), in amdgpu_ras_debugfs_table_read()
1178 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_debugfs_table_read()
1188 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_table_read() local
1195 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_table_read()
1231 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) in __verify_ras_table_checksum() argument
1233 struct amdgpu_device *adev = to_amdgpu_device(control); in __verify_ras_table_checksum()
1237 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) in __verify_ras_table_checksum()
1240 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in __verify_ras_table_checksum()
1243 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in __verify_ras_table_checksum()
1252 control->i2c_address + in __verify_ras_table_checksum()
1253 control->ras_header_offset, in __verify_ras_table_checksum()
1272 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) in __read_table_ras_info() argument
1274 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; in __read_table_ras_info()
1275 struct amdgpu_device *adev = to_amdgpu_device(control); in __read_table_ras_info()
1290 control->i2c_address + control->ras_info_offset, in __read_table_ras_info()
1305 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_init() argument
1308 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_init()
1310 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_init()
1323 if (!__get_eeprom_i2c_addr(adev, control)) in amdgpu_ras_eeprom_init()
1326 control->ras_header_offset = RAS_HDR_START; in amdgpu_ras_eeprom_init()
1327 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; in amdgpu_ras_eeprom_init()
1328 mutex_init(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_init()
1332 control->i2c_address + control->ras_header_offset, in amdgpu_ras_eeprom_init()
1342 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); in amdgpu_ras_eeprom_init()
1343 control->ras_record_offset = RAS_RECORD_START_V2_1; in amdgpu_ras_eeprom_init()
1344 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; in amdgpu_ras_eeprom_init()
1346 control->ras_num_recs = RAS_NUM_RECS(hdr); in amdgpu_ras_eeprom_init()
1347 control->ras_record_offset = RAS_RECORD_START; in amdgpu_ras_eeprom_init()
1348 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; in amdgpu_ras_eeprom_init()
1350 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); in amdgpu_ras_eeprom_init()
1354 control->ras_num_recs); in amdgpu_ras_eeprom_init()
1357 res = __read_table_ras_info(control); in amdgpu_ras_eeprom_init()
1362 res = __verify_ras_table_checksum(control); in amdgpu_ras_eeprom_init()
1369 if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_init()
1371 control->ras_num_recs, in amdgpu_ras_eeprom_init()
1376 res = __read_table_ras_info(control); in amdgpu_ras_eeprom_init()
1381 res = __verify_ras_table_checksum(control); in amdgpu_ras_eeprom_init()
1385 if (ras->bad_page_cnt_threshold > control->ras_num_recs) { in amdgpu_ras_eeprom_init()
1395 control->ras_num_recs, in amdgpu_ras_eeprom_init()
1397 res = amdgpu_ras_eeprom_correct_header_tag(control, in amdgpu_ras_eeprom_init()
1401 control->ras_num_recs, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_init()
1410 control->ras_num_recs, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_init()
1416 res = amdgpu_ras_eeprom_reset_table(control); in amdgpu_ras_eeprom_init()