54 	struct ep93xx_gpio_irq_chip	*eic;  member
68 	return egc->eic;  in to_ep93xx_gpio_irq_chip()
83 					  struct ep93xx_gpio_irq_chip *eic)  in ep93xx_gpio_update_int_params()  argument
85 	writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);  in ep93xx_gpio_update_int_params()
87 	writeb_relaxed(eic->int_type2,  in ep93xx_gpio_update_int_params()
88 		       epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);  in ep93xx_gpio_update_int_params()
90 	writeb_relaxed(eic->int_type1,  in ep93xx_gpio_update_int_params()
91 		       epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);  in ep93xx_gpio_update_int_params()
93 	writeb_relaxed(eic->int_unmasked & eic->int_enabled,  in ep93xx_gpio_update_int_params()
94 		       epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);  in ep93xx_gpio_update_int_params()
101 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_int_debounce()  local
105 		eic->int_debounce |= port_mask;  in ep93xx_gpio_int_debounce()
107 		eic->int_debounce &= ~port_mask;  in ep93xx_gpio_int_debounce()
109 	writeb(eic->int_debounce,  in ep93xx_gpio_int_debounce()
110 	       epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);  in ep93xx_gpio_int_debounce()
162 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_ack()  local
167 		eic->int_type2 ^= port_mask; /* switch edge direction */  in ep93xx_gpio_irq_ack()
168 		ep93xx_gpio_update_int_params(epg, eic);  in ep93xx_gpio_irq_ack()
171 	writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);  in ep93xx_gpio_irq_ack()
177 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_mask_ack()  local
182 		eic->int_type2 ^= port_mask; /* switch edge direction */  in ep93xx_gpio_irq_mask_ack()
184 	eic->int_unmasked &= ~port_mask;  in ep93xx_gpio_irq_mask_ack()
185 	ep93xx_gpio_update_int_params(epg, eic);  in ep93xx_gpio_irq_mask_ack()
187 	writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);  in ep93xx_gpio_irq_mask_ack()
194 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_mask()  local
197 	eic->int_unmasked &= ~BIT(d->irq & 7);  in ep93xx_gpio_irq_mask()
198 	ep93xx_gpio_update_int_params(epg, eic);  in ep93xx_gpio_irq_mask()
205 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_unmask()  local
209 	eic->int_unmasked |= BIT(d->irq & 7);  in ep93xx_gpio_irq_unmask()
210 	ep93xx_gpio_update_int_params(epg, eic);  in ep93xx_gpio_irq_unmask()
221 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_type()  local
231 		eic->int_type1 |= port_mask;  in ep93xx_gpio_irq_type()
232 		eic->int_type2 |= port_mask;  in ep93xx_gpio_irq_type()
236 		eic->int_type1 |= port_mask;  in ep93xx_gpio_irq_type()
237 		eic->int_type2 &= ~port_mask;  in ep93xx_gpio_irq_type()
241 		eic->int_type1 &= ~port_mask;  in ep93xx_gpio_irq_type()
242 		eic->int_type2 |= port_mask;  in ep93xx_gpio_irq_type()
246 		eic->int_type1 &= ~port_mask;  in ep93xx_gpio_irq_type()
247 		eic->int_type2 &= ~port_mask;  in ep93xx_gpio_irq_type()
251 		eic->int_type1 |= port_mask;  in ep93xx_gpio_irq_type()
254 			eic->int_type2 &= ~port_mask; /* falling */  in ep93xx_gpio_irq_type()
256 			eic->int_type2 |= port_mask; /* rising */  in ep93xx_gpio_irq_type()
265 	eic->int_enabled |= port_mask;  in ep93xx_gpio_irq_type()
267 	ep93xx_gpio_update_int_params(epg, eic);  in ep93xx_gpio_irq_type()
367 		egc->eic = devm_kcalloc(dev, 1,  in ep93xx_gpio_add_bank()
368 					sizeof(*egc->eic),  in ep93xx_gpio_add_bank()
370 		if (!egc->eic)  in ep93xx_gpio_add_bank()
372 		egc->eic->irq_offset = bank->irq;  in ep93xx_gpio_add_bank()