Lines Matching refs:offset
139 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset, in sprd_eic_update() argument
144 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); in sprd_eic_update()
152 tmp |= BIT(SPRD_EIC_BIT(offset)); in sprd_eic_update()
154 tmp &= ~BIT(SPRD_EIC_BIT(offset)); in sprd_eic_update()
160 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg) in sprd_eic_read() argument
164 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); in sprd_eic_read()
166 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset))); in sprd_eic_read()
169 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset) in sprd_eic_request() argument
171 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1); in sprd_eic_request()
175 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset) in sprd_eic_free() argument
177 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0); in sprd_eic_free()
180 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset) in sprd_eic_get() argument
186 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA); in sprd_eic_get()
188 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA); in sprd_eic_get()
190 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA); in sprd_eic_get()
196 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset) in sprd_eic_direction_input() argument
202 static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value) in sprd_eic_set() argument
207 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset, in sprd_eic_set_debounce() argument
212 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); in sprd_eic_set_debounce()
213 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4; in sprd_eic_set_debounce()
222 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset, in sprd_eic_set_config() argument
229 return sprd_eic_set_debounce(chip, offset, arg); in sprd_eic_set_config()
238 u32 offset = irqd_to_hwirq(data); in sprd_eic_irq_mask() local
242 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0); in sprd_eic_irq_mask()
243 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0); in sprd_eic_irq_mask()
246 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0); in sprd_eic_irq_mask()
249 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0); in sprd_eic_irq_mask()
252 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0); in sprd_eic_irq_mask()
258 gpiochip_disable_irq(chip, offset); in sprd_eic_irq_mask()
265 u32 offset = irqd_to_hwirq(data); in sprd_eic_irq_unmask() local
267 gpiochip_enable_irq(chip, offset); in sprd_eic_irq_unmask()
271 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1); in sprd_eic_irq_unmask()
272 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1); in sprd_eic_irq_unmask()
275 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1); in sprd_eic_irq_unmask()
278 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1); in sprd_eic_irq_unmask()
281 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1); in sprd_eic_irq_unmask()
292 u32 offset = irqd_to_hwirq(data); in sprd_eic_irq_ack() local
296 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); in sprd_eic_irq_ack()
299 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); in sprd_eic_irq_ack()
302 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); in sprd_eic_irq_ack()
305 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); in sprd_eic_irq_ack()
316 u32 offset = irqd_to_hwirq(data); in sprd_eic_irq_set_type() local
323 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); in sprd_eic_irq_set_type()
324 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); in sprd_eic_irq_set_type()
327 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); in sprd_eic_irq_set_type()
328 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); in sprd_eic_irq_set_type()
333 state = sprd_eic_get(chip, offset); in sprd_eic_irq_set_type()
335 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
337 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
340 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
342 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
355 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); in sprd_eic_irq_set_type()
356 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); in sprd_eic_irq_set_type()
359 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); in sprd_eic_irq_set_type()
360 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); in sprd_eic_irq_set_type()
365 state = sprd_eic_get(chip, offset); in sprd_eic_irq_set_type()
367 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
369 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
372 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
374 sprd_eic_update(chip, offset, in sprd_eic_irq_set_type()
387 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
388 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); in sprd_eic_irq_set_type()
389 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); in sprd_eic_irq_set_type()
390 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); in sprd_eic_irq_set_type()
394 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
395 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); in sprd_eic_irq_set_type()
396 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); in sprd_eic_irq_set_type()
397 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); in sprd_eic_irq_set_type()
401 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); in sprd_eic_irq_set_type()
402 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1); in sprd_eic_irq_set_type()
403 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); in sprd_eic_irq_set_type()
407 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
408 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); in sprd_eic_irq_set_type()
409 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); in sprd_eic_irq_set_type()
410 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); in sprd_eic_irq_set_type()
414 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
415 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); in sprd_eic_irq_set_type()
416 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); in sprd_eic_irq_set_type()
417 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); in sprd_eic_irq_set_type()
427 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
428 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); in sprd_eic_irq_set_type()
429 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); in sprd_eic_irq_set_type()
430 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); in sprd_eic_irq_set_type()
434 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
435 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); in sprd_eic_irq_set_type()
436 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); in sprd_eic_irq_set_type()
437 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); in sprd_eic_irq_set_type()
441 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); in sprd_eic_irq_set_type()
442 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1); in sprd_eic_irq_set_type()
443 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); in sprd_eic_irq_set_type()
447 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
448 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); in sprd_eic_irq_set_type()
449 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); in sprd_eic_irq_set_type()
450 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); in sprd_eic_irq_set_type()
454 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); in sprd_eic_irq_set_type()
455 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); in sprd_eic_irq_set_type()
456 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); in sprd_eic_irq_set_type()
457 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); in sprd_eic_irq_set_type()
473 unsigned int offset) in sprd_eic_toggle_trigger() argument
490 state = sprd_eic_get(chip, offset); in sprd_eic_toggle_trigger()
496 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); in sprd_eic_toggle_trigger()
498 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); in sprd_eic_toggle_trigger()
502 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); in sprd_eic_toggle_trigger()
504 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); in sprd_eic_toggle_trigger()
511 post_state = sprd_eic_get(chip, offset); in sprd_eic_toggle_trigger()
560 u32 offset = bank * SPRD_EIC_PER_BANK_NR + n; in sprd_eic_handle_one_type() local
562 girq = irq_find_mapping(chip->irq.domain, offset); in sprd_eic_handle_one_type()
565 sprd_eic_toggle_trigger(chip, girq, offset); in sprd_eic_handle_one_type()