135 #define dram_rw(pvt, i)			((u8)(pvt->ranges[i].base.lo & 0x3))  argument
136 #define dram_intlv_sel(pvt, i)		((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))  argument
137 #define dram_dst_node(pvt, i)		((u8)(pvt->ranges[i].lim.lo & 0x7))  argument
140 #define dhar_mem_hoist_valid(pvt)	((pvt)->dhar & BIT(1))  argument
141 #define dhar_base(pvt)			((pvt)->dhar & 0xff000000)  argument
142 #define k8_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff00) << 16)  argument
145 #define f10_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff80) << 16)  argument
166 #define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)]     & DCSB_CS_ENABLE)  argument
167 #define csrow_sec_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)  argument
189 #define dct_high_range_enabled(pvt)	((pvt)->dct_sel_lo & BIT(0))  argument
190 #define dct_interleave_enabled(pvt)	((pvt)->dct_sel_lo & BIT(2))  argument
192 #define dct_ganging_enabled(pvt)	((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))  argument
194 #define dct_data_intlv_enabled(pvt)	((pvt)->dct_sel_lo & BIT(5))  argument
195 #define dct_memory_cleared(pvt)		((pvt)->dct_sel_lo & BIT(10))  argument
219 #define online_spare_swap_done(pvt, c)	(((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)  argument
220 #define online_spare_bad_dramcs(pvt, c)	(((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)  argument
414 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)  in get_dram_base()  argument
416 	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;  in get_dram_base()
421 	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;  in get_dram_base()
424 static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)  in get_dram_limit()  argument
426 	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;  in get_dram_limit()
431 	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;  in get_dram_limit()
439 static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)  in dct_sel_interleave_addr()  argument
441 	if (pvt->fam == 0x15 && pvt->model >= 0x30)  in dct_sel_interleave_addr()
442 		return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |  in dct_sel_interleave_addr()
443 			((pvt->dct_sel_lo >> 6) & 0x3);  in dct_sel_interleave_addr()
445 	return	((pvt)->dct_sel_lo >> 6) & 0x3;  in dct_sel_interleave_addr()
467 	int  (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct,
469 	int (*hw_info_get)(struct amd64_pvt *pvt);
470 	bool (*ecc_enabled)(struct amd64_pvt *pvt);
472 	void (*dump_misc_regs)(struct amd64_pvt *pvt);
501 static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)  in dram_intlv_en()  argument
503 	if (pvt->fam == 0x15 && pvt->model >= 0x30) {  in dram_intlv_en()
505 		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);  in dram_intlv_en()
508 	return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;  in dram_intlv_en()
511 static inline u8 dhar_valid(struct amd64_pvt *pvt)  in dhar_valid()  argument
513 	if (pvt->fam == 0x15 && pvt->model >= 0x30) {  in dhar_valid()
515 		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);  in dhar_valid()
518 	return (pvt)->dhar & BIT(0);  in dhar_valid()
521 static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)  in dct_sel_baseaddr()  argument
523 	if (pvt->fam == 0x15 && pvt->model >= 0x30) {  in dct_sel_baseaddr()
525 		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);  in dct_sel_baseaddr()
528 	return (pvt)->dct_sel_lo & 0xFFFFF800;  in dct_sel_baseaddr()