1372 	int dimm, size0, size1;  in dct_debug_display_dimm_sizes()  local
1398 	for (dimm = 0; dimm < 4; dimm++) {  in dct_debug_display_dimm_sizes()
1400 		if (dcsb[dimm * 2] & DCSB_CS_ENABLE)  in dct_debug_display_dimm_sizes()
1408 						     DBAM_DIMM(dimm, dbam),  in dct_debug_display_dimm_sizes()
1409 						     dimm);  in dct_debug_display_dimm_sizes()
1412 		if (dcsb[dimm * 2 + 1] & DCSB_CS_ENABLE)  in dct_debug_display_dimm_sizes()
1414 						     DBAM_DIMM(dimm, dbam),  in dct_debug_display_dimm_sizes()
1415 						     dimm);  in dct_debug_display_dimm_sizes()
1418 			   dimm * 2,     size0,  in dct_debug_display_dimm_sizes()
1419 			   dimm * 2 + 1, size1);  in dct_debug_display_dimm_sizes()
1465 static int umc_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt)  in umc_get_cs_mode()  argument
1470 	if (csrow_enabled(2 * dimm, ctrl, pvt))  in umc_get_cs_mode()
1473 	if (csrow_enabled(2 * dimm + 1, ctrl, pvt))  in umc_get_cs_mode()
1477 	if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt))  in umc_get_cs_mode()
1498 				  int csrow_nr, int dimm)  in __addr_mask_to_cs_size()  argument
1522 	edac_dbg(1, "CS%d DIMM%d AddrMasks:\n", csrow_nr, dimm);  in __addr_mask_to_cs_size()
1538 	int dimm, size = 0;  in umc_addr_mask_to_cs_size()  local
1570 	dimm = csrow_nr >> 1;  in umc_addr_mask_to_cs_size()
1581 	return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, dimm);  in umc_addr_mask_to_cs_size()
1586 	int dimm, size0, size1, cs0, cs1, cs_mode;  in umc_debug_display_dimm_sizes()  local
1590 	for (dimm = 0; dimm < 2; dimm++) {  in umc_debug_display_dimm_sizes()
1591 		cs0 = dimm * 2;  in umc_debug_display_dimm_sizes()
1592 		cs1 = dimm * 2 + 1;  in umc_debug_display_dimm_sizes()
1594 		cs_mode = umc_get_cs_mode(dimm, ctrl, pvt);  in umc_debug_display_dimm_sizes()
3329 	struct dimm_info *dimm;  in umc_init_csrows()  local
3350 			dimm = mci->csrows[cs]->channels[umc]->dimm;  in umc_init_csrows()
3355 			dimm->nr_pages = umc_get_csrow_nr_pages(pvt, umc, cs);  in umc_init_csrows()
3356 			dimm->mtype = pvt->umc[umc].dram_type;  in umc_init_csrows()
3357 			dimm->edac_mode = edac_mode;  in umc_init_csrows()
3358 			dimm->dtype = dev_type;  in umc_init_csrows()
3359 			dimm->grain = 64;  in umc_init_csrows()
3373 	struct dimm_info *dimm;  in dct_init_csrows()  local
3406 			csrow->channels[0]->dimm->nr_pages = nr_pages;  in dct_init_csrows()
3413 			csrow->channels[1]->dimm->nr_pages = row_dct1_pages;  in dct_init_csrows()
3427 			dimm = csrow->channels[j]->dimm;  in dct_init_csrows()
3428 			dimm->mtype = pvt->dram_type;  in dct_init_csrows()
3429 			dimm->edac_mode = edac_mode;  in dct_init_csrows()
3430 			dimm->grain = 64;  in dct_init_csrows()
3839 	struct dimm_info *dimm;  in gpu_init_csrows()  local
3847 			dimm = mci->csrows[umc]->channels[cs]->dimm;  in gpu_init_csrows()
3852 			dimm->nr_pages = gpu_get_csrow_nr_pages(pvt, umc, cs);  in gpu_init_csrows()
3853 			dimm->edac_mode = EDAC_SECDED;  in gpu_init_csrows()
3854 			dimm->mtype = MEM_HBM2;  in gpu_init_csrows()
3855 			dimm->dtype = DEV_X16;  in gpu_init_csrows()
3856 			dimm->grain = 64;  in gpu_init_csrows()