Lines Matching refs:and
4 # Licensed and distributed under the GPL
40 levels are 0-4 (from low to high) and by default it is set to 2.
69 It should be noticed that keeping both GHES and a hardware-driven
82 Support for error detection and correction of DRAM ECC errors on
88 AMD CPUs up to and excluding family 0x17 provide for Memory
90 module allows the operator/user to inject Uncorrectable and
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
107 Support for error detection and correction for Amazon's Annapurna
108 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
114 Support for error detection and correction on the AMD 76x
121 Support for error detection and correction on the Intel
122 E7205, E7500, E7501 and E7505 server chipsets.
125 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
128 Support for error detection and correction on the Intel
136 Support for error detection and correction on the Intel
143 Support for error detection and correction on the Intel
144 DP82785P and E7210 server chipsets.
150 Support for error detection and correction on the Intel
157 Support for error detection and correction on the Intel
158 3000 and 3010 server chipsets.
164 Support for error detection and correction on the Intel
165 3200 and 3210 server chipsets.
171 Support for error detection and correction on the Intel
178 Support for error detection and correction on the Intel
185 Support for error detection and correction the Intel
192 Support for error detection and correction the Intel
195 and Xeon 55xx processors.
201 Support for error detection and correction on the Intel
208 Support for error detection and correction on the Radisys
216 Support for error detection and correction the Intel
223 Support for error detection and correction the Intel
230 Support for error detection and correction the Intel
237 Support for error detection and correction the Intel
238 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
247 Support for error detection and correction the Intel
259 Support for error detection and correction the Intel
269 Support for error detection and correction on the Intel
271 first used on the Apollo Lake platform and Denverton
279 Support for error detection and correction on the Intel
288 Support for error detection and correction on the Freescale
295 Support for error detection and correction on Freescale memory
302 Support for error detection and correction on PA Semi
309 Support for error detection and correction on the
320 440SP, 440SPe, 460EX, 460GT and 460SX.
326 Support for error detection and correction on the
335 Support for error detection and correction on the
344 Support for error detection and correction on the
345 IBM CPC925 Bridge and Memory Controller, which is
353 Support for error detection and correction on the
360 Support for error detection and correction on the
367 Support for error detection and correction on the primary caches of
374 Support for error detection and correction on the
381 Support for error detection and correction on the
388 Support for error detection and correction on the
396 Support for error detection and correction on the
398 Coherent Processor Interconnect (CCPI) and L2 cache
405 Support for error detection and correction on the
413 Support for error detection and correction on the
422 Support for error detection and correction on the
430 Support for error detection and correction on the
437 Support for error detection and correction on the
444 Support for error detection and correction on the
451 Support for error detection and correction on the
458 Support for error detection and correction on the
465 Support for error detection and correction on the
472 Support for error detection and correction on the
479 Support for error detection and correction on the SiFive SoCs.
482 bool "Marvell Armada XP DDR and L2 Cache ECC"
485 Support for error correction and detection on the Marvell Aramada XP
486 DDR RAM and L2 cache controllers.
492 Support for error detection and correction on the Synopsys DDR
499 Support for error detection and correction on the
506 Support for error detection and correction on the TI SoCs.
512 Support for error detection and correction on the
515 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
517 of Tag RAM and Data RAM.
519 For debugging issues having to do with stability and overall system
526 Support for error detection and correction on the Aspeed AST BMC SoC.
535 Support for error detection and correction on the
542 Support for error detection and correction on the
549 This driver supports error detection and correction for the
557 Support for error detection and correction on the Nuvoton NPCM DDR