Lines Matching refs:ad
150 static int admac_alloc_sram_carveout(struct admac_data *ad, in admac_alloc_sram_carveout() argument
158 sram = &ad->txcache; in admac_alloc_sram_carveout()
160 sram = &ad->rxcache; in admac_alloc_sram_carveout()
162 mutex_lock(&ad->cache_alloc_lock); in admac_alloc_sram_carveout()
177 mutex_unlock(&ad->cache_alloc_lock); in admac_alloc_sram_carveout()
182 static void admac_free_sram_carveout(struct admac_data *ad, in admac_free_sram_carveout() argument
191 sram = &ad->txcache; in admac_free_sram_carveout()
193 sram = &ad->rxcache; in admac_free_sram_carveout()
198 mutex_lock(&ad->cache_alloc_lock); in admac_free_sram_carveout()
201 mutex_unlock(&ad->cache_alloc_lock); in admac_free_sram_carveout()
204 static void admac_modify(struct admac_data *ad, int reg, u32 mask, u32 val) in admac_modify() argument
206 void __iomem *addr = ad->base + reg; in admac_modify()
285 static void admac_cyclic_write_one_desc(struct admac_data *ad, int channo, in admac_cyclic_write_one_desc() argument
295 dev_dbg(ad->dev, "ch%d descriptor: addr=0x%pad len=0x%zx flags=0x%lx\n", in admac_cyclic_write_one_desc()
298 writel_relaxed(lower_32_bits(addr), ad->base + REG_DESC_WRITE(channo)); in admac_cyclic_write_one_desc()
299 writel_relaxed(upper_32_bits(addr), ad->base + REG_DESC_WRITE(channo)); in admac_cyclic_write_one_desc()
300 writel_relaxed(tx->period_len, ad->base + REG_DESC_WRITE(channo)); in admac_cyclic_write_one_desc()
301 writel_relaxed(FLAG_DESC_NOTIFY, ad->base + REG_DESC_WRITE(channo)); in admac_cyclic_write_one_desc()
311 static void admac_cyclic_write_desc(struct admac_data *ad, int channo, in admac_cyclic_write_desc() argument
317 if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_FULL) in admac_cyclic_write_desc()
319 admac_cyclic_write_one_desc(ad, channo, tx); in admac_cyclic_write_desc()
343 static u32 admac_cyclic_read_residue(struct admac_data *ad, int channo, in admac_cyclic_read_residue() argument
351 ring1 = readl_relaxed(ad->base + REG_REPORT_RING(channo)); in admac_cyclic_read_residue()
352 residue1 = readl_relaxed(ad->base + REG_RESIDUE(channo)); in admac_cyclic_read_residue()
353 ring2 = readl_relaxed(ad->base + REG_REPORT_RING(channo)); in admac_cyclic_read_residue()
354 residue2 = readl_relaxed(ad->base + REG_RESIDUE(channo)); in admac_cyclic_read_residue()
376 struct admac_data *ad = adchan->host; in admac_tx_status() local
392 residue = admac_cyclic_read_residue(ad, adchan->no, adtx); in admac_tx_status()
411 struct admac_data *ad = adchan->host; in admac_start_chan() local
415 ad->base + REG_CHAN_INTSTATUS(adchan->no, ad->irq_index)); in admac_start_chan()
417 ad->base + REG_CHAN_INTMASK(adchan->no, ad->irq_index)); in admac_start_chan()
421 writel_relaxed(startbit, ad->base + REG_TX_START); in admac_start_chan()
424 writel_relaxed(startbit, ad->base + REG_RX_START); in admac_start_chan()
434 struct admac_data *ad = adchan->host; in admac_stop_chan() local
439 writel_relaxed(stopbit, ad->base + REG_TX_STOP); in admac_stop_chan()
442 writel_relaxed(stopbit, ad->base + REG_RX_STOP); in admac_stop_chan()
452 struct admac_data *ad = adchan->host; in admac_reset_rings() local
455 ad->base + REG_CHAN_CTL(adchan->no)); in admac_reset_rings()
456 writel_relaxed(0, ad->base + REG_CHAN_CTL(adchan->no)); in admac_reset_rings()
461 struct admac_data *ad = adchan->host; in admac_start_current_tx() local
465 writel_relaxed(0, ad->base + REG_CHAN_CTL(ch)); in admac_start_current_tx()
467 admac_cyclic_write_one_desc(ad, ch, adchan->current_tx); in admac_start_current_tx()
469 admac_cyclic_write_desc(ad, ch, adchan->current_tx); in admac_start_current_tx()
555 struct admac_data *ad = adchan->host; in admac_alloc_chan_resources() local
559 ret = admac_alloc_sram_carveout(ad, admac_chan_direction(adchan->no), in admac_alloc_chan_resources()
565 ad->base + REG_CHAN_SRAM_CARVEOUT(adchan->no)); in admac_alloc_chan_resources()
582 struct admac_data *ad = (struct admac_data *) ofdma->of_dma_data; in admac_dma_of_xlate() local
590 if (index >= ad->nchannels) { in admac_dma_of_xlate()
591 dev_err(ad->dev, "channel index %u out of bounds\n", index); in admac_dma_of_xlate()
595 return dma_get_slave_channel(&ad->channels[index].chan); in admac_dma_of_xlate()
598 static int admac_drain_reports(struct admac_data *ad, int channo) in admac_drain_reports() argument
605 if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_EMPTY) in admac_drain_reports()
608 countval_lo = readl_relaxed(ad->base + REG_REPORT_READ(channo)); in admac_drain_reports()
609 countval_hi = readl_relaxed(ad->base + REG_REPORT_READ(channo)); in admac_drain_reports()
610 unk1 = readl_relaxed(ad->base + REG_REPORT_READ(channo)); in admac_drain_reports()
611 flags = readl_relaxed(ad->base + REG_REPORT_READ(channo)); in admac_drain_reports()
613 dev_dbg(ad->dev, "ch%d report: countval=0x%llx unk1=0x%x flags=0x%x\n", in admac_drain_reports()
620 static void admac_handle_status_err(struct admac_data *ad, int channo) in admac_handle_status_err() argument
624 if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_ERR) { in admac_handle_status_err()
625 writel_relaxed(RING_ERR, ad->base + REG_DESC_RING(channo)); in admac_handle_status_err()
626 dev_err_ratelimited(ad->dev, "ch%d descriptor ring error\n", channo); in admac_handle_status_err()
630 if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_ERR) { in admac_handle_status_err()
631 writel_relaxed(RING_ERR, ad->base + REG_REPORT_RING(channo)); in admac_handle_status_err()
632 dev_err_ratelimited(ad->dev, "ch%d report ring error\n", channo); in admac_handle_status_err()
637 dev_err(ad->dev, "ch%d unknown error, masking errors as cause of IRQs\n", channo); in admac_handle_status_err()
638 admac_modify(ad, REG_CHAN_INTMASK(channo, ad->irq_index), in admac_handle_status_err()
643 static void admac_handle_status_desc_done(struct admac_data *ad, int channo) in admac_handle_status_desc_done() argument
645 struct admac_chan *adchan = &ad->channels[channo]; in admac_handle_status_desc_done()
650 ad->base + REG_CHAN_INTSTATUS(channo, ad->irq_index)); in admac_handle_status_desc_done()
653 nreports = admac_drain_reports(ad, channo); in admac_handle_status_desc_done()
662 admac_cyclic_write_desc(ad, channo, tx); in admac_handle_status_desc_done()
668 static void admac_handle_chan_int(struct admac_data *ad, int no) in admac_handle_chan_int() argument
670 u32 cause = readl_relaxed(ad->base + REG_CHAN_INTSTATUS(no, ad->irq_index)); in admac_handle_chan_int()
673 admac_handle_status_err(ad, no); in admac_handle_chan_int()
676 admac_handle_status_desc_done(ad, no); in admac_handle_chan_int()
681 struct admac_data *ad = devid; in admac_interrupt() local
685 rx_intstate = readl_relaxed(ad->base + REG_RX_INTSTATE(ad->irq_index)); in admac_interrupt()
686 tx_intstate = readl_relaxed(ad->base + REG_TX_INTSTATE(ad->irq_index)); in admac_interrupt()
687 global_intstate = readl_relaxed(ad->base + REG_GLOBAL_INTSTATE(ad->irq_index)); in admac_interrupt()
692 for (i = 0; i < ad->nchannels; i += 2) { in admac_interrupt()
694 admac_handle_chan_int(ad, i); in admac_interrupt()
698 for (i = 1; i < ad->nchannels; i += 2) { in admac_interrupt()
700 admac_handle_chan_int(ad, i); in admac_interrupt()
705 dev_warn(ad->dev, "clearing unknown global interrupt flag: %x\n", in admac_interrupt()
707 writel_relaxed(~(u32) 0, ad->base + REG_GLOBAL_INTSTATE(ad->irq_index)); in admac_interrupt()
742 struct admac_data *ad = adchan->host; in admac_device_config() local
745 u32 bus_width = readl_relaxed(ad->base + REG_BUS_WIDTH(adchan->no)) & in admac_device_config()
785 writel_relaxed(bus_width, ad->base + REG_BUS_WIDTH(adchan->no)); in admac_device_config()
796 ad->base + REG_CHAN_FIFOCTL(adchan->no)); in admac_device_config()
804 struct admac_data *ad; in admac_probe() local
815 ad = devm_kzalloc(&pdev->dev, struct_size(ad, channels, nchannels), GFP_KERNEL); in admac_probe()
816 if (!ad) in admac_probe()
819 platform_set_drvdata(pdev, ad); in admac_probe()
820 ad->dev = &pdev->dev; in admac_probe()
821 ad->nchannels = nchannels; in admac_probe()
822 mutex_init(&ad->cache_alloc_lock); in admac_probe()
831 ad->irq_index = i; in admac_probe()
838 ad->irq = irq; in admac_probe()
840 ad->base = devm_platform_ioremap_resource(pdev, 0); in admac_probe()
841 if (IS_ERR(ad->base)) in admac_probe()
842 return dev_err_probe(&pdev->dev, PTR_ERR(ad->base), in admac_probe()
845 ad->rstc = devm_reset_control_get_optional_shared(&pdev->dev, NULL); in admac_probe()
846 if (IS_ERR(ad->rstc)) in admac_probe()
847 return PTR_ERR(ad->rstc); in admac_probe()
849 dma = &ad->dma; in admac_probe()
877 struct admac_chan *adchan = &ad->channels[i]; in admac_probe()
879 adchan->host = ad; in admac_probe()
881 adchan->chan.device = &ad->dma; in admac_probe()
890 err = reset_control_reset(ad->rstc); in admac_probe()
895 err = request_irq(irq, admac_interrupt, 0, dev_name(&pdev->dev), ad); in admac_probe()
902 err = dma_async_device_register(&ad->dma); in admac_probe()
908 err = of_dma_controller_register(pdev->dev.of_node, admac_dma_of_xlate, ad); in admac_probe()
910 dma_async_device_unregister(&ad->dma); in admac_probe()
915 ad->txcache.size = readl_relaxed(ad->base + REG_TX_SRAM_SIZE); in admac_probe()
916 ad->rxcache.size = readl_relaxed(ad->base + REG_RX_SRAM_SIZE); in admac_probe()
920 readl_relaxed(ad->base + REG_IMPRINT), ad->txcache.size, ad->rxcache.size); in admac_probe()
925 free_irq(ad->irq, ad); in admac_probe()
927 reset_control_rearm(ad->rstc); in admac_probe()
933 struct admac_data *ad = platform_get_drvdata(pdev); in admac_remove() local
936 dma_async_device_unregister(&ad->dma); in admac_remove()
937 free_irq(ad->irq, ad); in admac_remove()
938 reset_control_rearm(ad->rstc); in admac_remove()