125 #define SET_CAP_CSR(handle, csr, val) \  argument
126 	ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
127 #define GET_CAP_CSR(handle, csr) \  argument
128 	ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
129 #define AE_CSR(handle, ae) \  argument
130 	((char __iomem *)(handle)->hal_cap_ae_local_csr_addr_v + ((ae) << 12))
131 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr)))  argument
132 #define SET_AE_CSR(handle, ae, csr, val) \  argument
133 	ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)  argument
135 #define AE_XFER(handle, ae) \  argument
136 	((char __iomem *)(handle)->hal_cap_ae_xfer_csr_addr_v + ((ae) << 12))
137 #define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \  argument
139 #define SET_AE_XFER(handle, ae, reg, val) \  argument
140 	ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
141 #define SRAM_WRITE(handle, addr, val) \  argument
142 	ADF_CSR_WR((handle)->hal_sram_addr_v, addr, val)