39 	struct sh_tmu_device *tmu;  member
89 		switch (ch->tmu->model) {  in sh_tmu_read()
91 			return ioread8(ch->tmu->mapbase + 2);  in sh_tmu_read()
93 			return ioread8(ch->tmu->mapbase + 4);  in sh_tmu_read()
111 		switch (ch->tmu->model) {  in sh_tmu_write()
113 			return iowrite8(value, ch->tmu->mapbase + 2);  in sh_tmu_write()
115 			return iowrite8(value, ch->tmu->mapbase + 4);  in sh_tmu_write()
132 	raw_spin_lock_irqsave(&ch->tmu->lock, flags);  in sh_tmu_start_stop_ch()
141 	raw_spin_unlock_irqrestore(&ch->tmu->lock, flags);  in sh_tmu_start_stop_ch()
149 	ret = clk_enable(ch->tmu->clk);  in __sh_tmu_enable()
151 		dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",  in __sh_tmu_enable()
177 	pm_runtime_get_sync(&ch->tmu->pdev->dev);  in sh_tmu_enable()
178 	dev_pm_syscore_device(&ch->tmu->pdev->dev, true);  in sh_tmu_enable()
192 	clk_disable(ch->tmu->clk);  in __sh_tmu_disable()
205 	dev_pm_syscore_device(&ch->tmu->pdev->dev, false);  in sh_tmu_disable()
206 	pm_runtime_put(&ch->tmu->pdev->dev);  in sh_tmu_disable()
295 		dev_pm_genpd_suspend(&ch->tmu->pdev->dev);  in sh_tmu_clocksource_suspend()
307 		dev_pm_genpd_resume(&ch->tmu->pdev->dev);  in sh_tmu_clocksource_resume()
327 	dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",  in sh_tmu_register_clocksource()
330 	clocksource_register_hz(cs, ch->tmu->rate);  in sh_tmu_register_clocksource()
344 		ch->periodic = (ch->tmu->rate + HZ/2) / HZ;  in sh_tmu_clock_event_start()
367 	dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n",  in sh_tmu_clock_event_set_state()
397 	dev_pm_genpd_suspend(&ced_to_sh_tmu(ced)->tmu->pdev->dev);  in sh_tmu_clock_event_suspend()
402 	dev_pm_genpd_resume(&ced_to_sh_tmu(ced)->tmu->pdev->dev);  in sh_tmu_clock_event_resume()
423 	dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",  in sh_tmu_register_clockevent()
426 	clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff);  in sh_tmu_register_clockevent()
430 			  dev_name(&ch->tmu->pdev->dev), ch);  in sh_tmu_register_clockevent()
432 		dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",  in sh_tmu_register_clockevent()
442 		ch->tmu->has_clockevent = true;  in sh_tmu_register()
445 		ch->tmu->has_clocksource = true;  in sh_tmu_register()
454 				struct sh_tmu_device *tmu)  in sh_tmu_channel_setup()  argument
460 	ch->tmu = tmu;  in sh_tmu_channel_setup()
463 	if (tmu->model == SH_TMU_SH3)  in sh_tmu_channel_setup()
464 		ch->base = tmu->mapbase + 4 + ch->index * 12;  in sh_tmu_channel_setup()
466 		ch->base = tmu->mapbase + 8 + ch->index * 12;  in sh_tmu_channel_setup()
468 	ch->irq = platform_get_irq(tmu->pdev, index);  in sh_tmu_channel_setup()
475 	return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),  in sh_tmu_channel_setup()
479 static int sh_tmu_map_memory(struct sh_tmu_device *tmu)  in sh_tmu_map_memory()  argument
483 	res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);  in sh_tmu_map_memory()
485 		dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");  in sh_tmu_map_memory()
489 	tmu->mapbase = ioremap(res->start, resource_size(res));  in sh_tmu_map_memory()
490 	if (tmu->mapbase == NULL)  in sh_tmu_map_memory()
496 static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)  in sh_tmu_parse_dt()  argument
498 	struct device_node *np = tmu->pdev->dev.of_node;  in sh_tmu_parse_dt()
500 	tmu->model = SH_TMU;  in sh_tmu_parse_dt()
501 	tmu->num_channels = 3;  in sh_tmu_parse_dt()
503 	of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);  in sh_tmu_parse_dt()
505 	if (tmu->num_channels != 2 && tmu->num_channels != 3) {  in sh_tmu_parse_dt()
506 		dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",  in sh_tmu_parse_dt()
507 			tmu->num_channels);  in sh_tmu_parse_dt()
514 static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)  in sh_tmu_setup()  argument
519 	tmu->pdev = pdev;  in sh_tmu_setup()
521 	raw_spin_lock_init(&tmu->lock);  in sh_tmu_setup()
524 		ret = sh_tmu_parse_dt(tmu);  in sh_tmu_setup()
531 		tmu->model = id->driver_data;  in sh_tmu_setup()
532 		tmu->num_channels = hweight8(cfg->channels_mask);  in sh_tmu_setup()
534 		dev_err(&tmu->pdev->dev, "missing platform data\n");  in sh_tmu_setup()
539 	tmu->clk = clk_get(&tmu->pdev->dev, "fck");  in sh_tmu_setup()
540 	if (IS_ERR(tmu->clk)) {  in sh_tmu_setup()
541 		dev_err(&tmu->pdev->dev, "cannot get clock\n");  in sh_tmu_setup()
542 		return PTR_ERR(tmu->clk);  in sh_tmu_setup()
545 	ret = clk_prepare(tmu->clk);  in sh_tmu_setup()
550 	ret = clk_enable(tmu->clk);  in sh_tmu_setup()
554 	tmu->rate = clk_get_rate(tmu->clk) / 4;  in sh_tmu_setup()
555 	clk_disable(tmu->clk);  in sh_tmu_setup()
558 	ret = sh_tmu_map_memory(tmu);  in sh_tmu_setup()
560 		dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");  in sh_tmu_setup()
565 	tmu->channels = kcalloc(tmu->num_channels, sizeof(*tmu->channels),  in sh_tmu_setup()
567 	if (tmu->channels == NULL) {  in sh_tmu_setup()
576 	for (i = 0; i < tmu->num_channels; ++i) {  in sh_tmu_setup()
577 		ret = sh_tmu_channel_setup(&tmu->channels[i], i,  in sh_tmu_setup()
578 					   i == 0, i == 1, tmu);  in sh_tmu_setup()
583 	platform_set_drvdata(pdev, tmu);  in sh_tmu_setup()
588 	kfree(tmu->channels);  in sh_tmu_setup()
589 	iounmap(tmu->mapbase);  in sh_tmu_setup()
591 	clk_unprepare(tmu->clk);  in sh_tmu_setup()
593 	clk_put(tmu->clk);  in sh_tmu_setup()
599 	struct sh_tmu_device *tmu = platform_get_drvdata(pdev);  in sh_tmu_probe()  local
607 	if (tmu) {  in sh_tmu_probe()
612 	tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);  in sh_tmu_probe()
613 	if (tmu == NULL)  in sh_tmu_probe()
616 	ret = sh_tmu_setup(tmu, pdev);  in sh_tmu_probe()
618 		kfree(tmu);  in sh_tmu_probe()
627 	if (tmu->has_clockevent || tmu->has_clocksource)  in sh_tmu_probe()