Lines Matching refs:ch
84 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) in sh_tmu_read() argument
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
100 return ioread16(ch->base + offs); in sh_tmu_read()
102 return ioread32(ch->base + offs); in sh_tmu_read()
105 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr, in sh_tmu_write() argument
111 switch (ch->tmu->model) { in sh_tmu_write()
113 return iowrite8(value, ch->tmu->mapbase + 2); in sh_tmu_write()
115 return iowrite8(value, ch->tmu->mapbase + 4); in sh_tmu_write()
122 iowrite16(value, ch->base + offs); in sh_tmu_write()
124 iowrite32(value, ch->base + offs); in sh_tmu_write()
127 static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start) in sh_tmu_start_stop_ch() argument
132 raw_spin_lock_irqsave(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
133 value = sh_tmu_read(ch, TSTR); in sh_tmu_start_stop_ch()
136 value |= 1 << ch->index; in sh_tmu_start_stop_ch()
138 value &= ~(1 << ch->index); in sh_tmu_start_stop_ch()
140 sh_tmu_write(ch, TSTR, value); in sh_tmu_start_stop_ch()
141 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
144 static int __sh_tmu_enable(struct sh_tmu_channel *ch) in __sh_tmu_enable() argument
149 ret = clk_enable(ch->tmu->clk); in __sh_tmu_enable()
151 dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n", in __sh_tmu_enable()
152 ch->index); in __sh_tmu_enable()
157 sh_tmu_start_stop_ch(ch, 0); in __sh_tmu_enable()
160 sh_tmu_write(ch, TCOR, 0xffffffff); in __sh_tmu_enable()
161 sh_tmu_write(ch, TCNT, 0xffffffff); in __sh_tmu_enable()
164 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in __sh_tmu_enable()
167 sh_tmu_start_stop_ch(ch, 1); in __sh_tmu_enable()
172 static int sh_tmu_enable(struct sh_tmu_channel *ch) in sh_tmu_enable() argument
174 if (ch->enable_count++ > 0) in sh_tmu_enable()
177 pm_runtime_get_sync(&ch->tmu->pdev->dev); in sh_tmu_enable()
178 dev_pm_syscore_device(&ch->tmu->pdev->dev, true); in sh_tmu_enable()
180 return __sh_tmu_enable(ch); in sh_tmu_enable()
183 static void __sh_tmu_disable(struct sh_tmu_channel *ch) in __sh_tmu_disable() argument
186 sh_tmu_start_stop_ch(ch, 0); in __sh_tmu_disable()
189 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in __sh_tmu_disable()
192 clk_disable(ch->tmu->clk); in __sh_tmu_disable()
195 static void sh_tmu_disable(struct sh_tmu_channel *ch) in sh_tmu_disable() argument
197 if (WARN_ON(ch->enable_count == 0)) in sh_tmu_disable()
200 if (--ch->enable_count > 0) in sh_tmu_disable()
203 __sh_tmu_disable(ch); in sh_tmu_disable()
205 dev_pm_syscore_device(&ch->tmu->pdev->dev, false); in sh_tmu_disable()
206 pm_runtime_put(&ch->tmu->pdev->dev); in sh_tmu_disable()
209 static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, in sh_tmu_set_next() argument
213 sh_tmu_start_stop_ch(ch, 0); in sh_tmu_set_next()
216 sh_tmu_read(ch, TCR); in sh_tmu_set_next()
219 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); in sh_tmu_set_next()
223 sh_tmu_write(ch, TCOR, delta); in sh_tmu_set_next()
225 sh_tmu_write(ch, TCOR, 0xffffffff); in sh_tmu_set_next()
227 sh_tmu_write(ch, TCNT, delta); in sh_tmu_set_next()
230 sh_tmu_start_stop_ch(ch, 1); in sh_tmu_set_next()
235 struct sh_tmu_channel *ch = dev_id; in sh_tmu_interrupt() local
238 if (clockevent_state_oneshot(&ch->ced)) in sh_tmu_interrupt()
239 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in sh_tmu_interrupt()
241 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); in sh_tmu_interrupt()
244 ch->ced.event_handler(&ch->ced); in sh_tmu_interrupt()
255 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_read() local
257 return sh_tmu_read(ch, TCNT) ^ 0xffffffff; in sh_tmu_clocksource_read()
262 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_enable() local
265 if (WARN_ON(ch->cs_enabled)) in sh_tmu_clocksource_enable()
268 ret = sh_tmu_enable(ch); in sh_tmu_clocksource_enable()
270 ch->cs_enabled = true; in sh_tmu_clocksource_enable()
277 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_disable() local
279 if (WARN_ON(!ch->cs_enabled)) in sh_tmu_clocksource_disable()
282 sh_tmu_disable(ch); in sh_tmu_clocksource_disable()
283 ch->cs_enabled = false; in sh_tmu_clocksource_disable()
288 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_suspend() local
290 if (!ch->cs_enabled) in sh_tmu_clocksource_suspend()
293 if (--ch->enable_count == 0) { in sh_tmu_clocksource_suspend()
294 __sh_tmu_disable(ch); in sh_tmu_clocksource_suspend()
295 dev_pm_genpd_suspend(&ch->tmu->pdev->dev); in sh_tmu_clocksource_suspend()
301 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_resume() local
303 if (!ch->cs_enabled) in sh_tmu_clocksource_resume()
306 if (ch->enable_count++ == 0) { in sh_tmu_clocksource_resume()
307 dev_pm_genpd_resume(&ch->tmu->pdev->dev); in sh_tmu_clocksource_resume()
308 __sh_tmu_enable(ch); in sh_tmu_clocksource_resume()
312 static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, in sh_tmu_register_clocksource() argument
315 struct clocksource *cs = &ch->cs; in sh_tmu_register_clocksource()
327 dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n", in sh_tmu_register_clocksource()
328 ch->index); in sh_tmu_register_clocksource()
330 clocksource_register_hz(cs, ch->tmu->rate); in sh_tmu_register_clocksource()
339 static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic) in sh_tmu_clock_event_start() argument
341 sh_tmu_enable(ch); in sh_tmu_clock_event_start()
344 ch->periodic = (ch->tmu->rate + HZ/2) / HZ; in sh_tmu_clock_event_start()
345 sh_tmu_set_next(ch, ch->periodic, 1); in sh_tmu_clock_event_start()
351 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); in sh_tmu_clock_event_shutdown() local
354 sh_tmu_disable(ch); in sh_tmu_clock_event_shutdown()
361 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); in sh_tmu_clock_event_set_state() local
365 sh_tmu_disable(ch); in sh_tmu_clock_event_set_state()
367 dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n", in sh_tmu_clock_event_set_state()
368 ch->index, periodic ? "periodic" : "oneshot"); in sh_tmu_clock_event_set_state()
369 sh_tmu_clock_event_start(ch, periodic); in sh_tmu_clock_event_set_state()
386 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); in sh_tmu_clock_event_next() local
391 sh_tmu_set_next(ch, delta, 0); in sh_tmu_clock_event_next()
405 static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, in sh_tmu_register_clockevent() argument
408 struct clock_event_device *ced = &ch->ced; in sh_tmu_register_clockevent()
423 dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n", in sh_tmu_register_clockevent()
424 ch->index); in sh_tmu_register_clockevent()
426 clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff); in sh_tmu_register_clockevent()
428 ret = request_irq(ch->irq, sh_tmu_interrupt, in sh_tmu_register_clockevent()
430 dev_name(&ch->tmu->pdev->dev), ch); in sh_tmu_register_clockevent()
432 dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n", in sh_tmu_register_clockevent()
433 ch->index, ch->irq); in sh_tmu_register_clockevent()
438 static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name, in sh_tmu_register() argument
442 ch->tmu->has_clockevent = true; in sh_tmu_register()
443 sh_tmu_register_clockevent(ch, name); in sh_tmu_register()
445 ch->tmu->has_clocksource = true; in sh_tmu_register()
446 sh_tmu_register_clocksource(ch, name); in sh_tmu_register()
452 static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, in sh_tmu_channel_setup() argument
460 ch->tmu = tmu; in sh_tmu_channel_setup()
461 ch->index = index; in sh_tmu_channel_setup()
464 ch->base = tmu->mapbase + 4 + ch->index * 12; in sh_tmu_channel_setup()
466 ch->base = tmu->mapbase + 8 + ch->index * 12; in sh_tmu_channel_setup()
468 ch->irq = platform_get_irq(tmu->pdev, index); in sh_tmu_channel_setup()
469 if (ch->irq < 0) in sh_tmu_channel_setup()
470 return ch->irq; in sh_tmu_channel_setup()
472 ch->cs_enabled = false; in sh_tmu_channel_setup()
473 ch->enable_count = 0; in sh_tmu_channel_setup()
475 return sh_tmu_register(ch, dev_name(&tmu->pdev->dev), in sh_tmu_channel_setup()