Lines Matching refs:td
331 static inline u32 dfll_readl(struct tegra_dfll *td, u32 offs) in dfll_readl() argument
333 return __raw_readl(td->base + offs); in dfll_readl()
336 static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs) in dfll_writel() argument
339 __raw_writel(val, td->base + offs); in dfll_writel()
342 static inline void dfll_wmb(struct tegra_dfll *td) in dfll_wmb() argument
344 dfll_readl(td, DFLL_CTRL); in dfll_wmb()
349 static inline u32 dfll_i2c_readl(struct tegra_dfll *td, u32 offs) in dfll_i2c_readl() argument
351 return __raw_readl(td->i2c_base + offs); in dfll_i2c_readl()
354 static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs) in dfll_i2c_writel() argument
356 __raw_writel(val, td->i2c_base + offs); in dfll_i2c_writel()
359 static inline void dfll_i2c_wmb(struct tegra_dfll *td) in dfll_i2c_wmb() argument
361 dfll_i2c_readl(td, DFLL_I2C_CFG); in dfll_i2c_wmb()
371 static bool dfll_is_running(struct tegra_dfll *td) in dfll_is_running() argument
373 return td->mode >= DFLL_OPEN_LOOP; in dfll_is_running()
391 struct tegra_dfll *td = dev_get_drvdata(dev); in tegra_dfll_runtime_resume() local
394 ret = clk_enable(td->ref_clk); in tegra_dfll_runtime_resume()
400 ret = clk_enable(td->soc_clk); in tegra_dfll_runtime_resume()
403 clk_disable(td->ref_clk); in tegra_dfll_runtime_resume()
407 ret = clk_enable(td->i2c_clk); in tegra_dfll_runtime_resume()
410 clk_disable(td->soc_clk); in tegra_dfll_runtime_resume()
411 clk_disable(td->ref_clk); in tegra_dfll_runtime_resume()
428 struct tegra_dfll *td = dev_get_drvdata(dev); in tegra_dfll_runtime_suspend() local
430 clk_disable(td->ref_clk); in tegra_dfll_runtime_suspend()
431 clk_disable(td->soc_clk); in tegra_dfll_runtime_suspend()
432 clk_disable(td->i2c_clk); in tegra_dfll_runtime_suspend()
450 static void dfll_tune_low(struct tegra_dfll *td) in dfll_tune_low() argument
452 td->tune_range = DFLL_TUNE_LOW; in dfll_tune_low()
454 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0); in dfll_tune_low()
455 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1); in dfll_tune_low()
456 dfll_wmb(td); in dfll_tune_low()
458 if (td->soc->set_clock_trimmers_low) in dfll_tune_low()
459 td->soc->set_clock_trimmers_low(); in dfll_tune_low()
492 static void dfll_set_mode(struct tegra_dfll *td, in dfll_set_mode() argument
495 td->mode = mode; in dfll_set_mode()
496 dfll_writel(td, mode - 1, DFLL_CTRL); in dfll_set_mode()
497 dfll_wmb(td); in dfll_set_mode()
504 static unsigned long get_dvco_rate_below(struct tegra_dfll *td, u8 out_min) in get_dvco_rate_below() argument
510 min_uv = td->lut_uv[out_min]; in get_dvco_rate_below()
512 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); in get_dvco_rate_below()
540 static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable) in dfll_i2c_set_output_enabled() argument
544 val = dfll_i2c_readl(td, DFLL_OUTPUT_CFG); in dfll_i2c_set_output_enabled()
551 dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG); in dfll_i2c_set_output_enabled()
552 dfll_i2c_wmb(td); in dfll_i2c_set_output_enabled()
571 static int dfll_pwm_set_output_enabled(struct tegra_dfll *td, bool enable) in dfll_pwm_set_output_enabled() argument
577 ret = pinctrl_select_state(td->pwm_pin, td->pwm_enable_state); in dfll_pwm_set_output_enabled()
579 dev_err(td->dev, "setting enable state failed\n"); in dfll_pwm_set_output_enabled()
582 val = dfll_readl(td, DFLL_OUTPUT_CFG); in dfll_pwm_set_output_enabled()
584 div = DIV_ROUND_UP(td->ref_rate, td->pwm_rate); in dfll_pwm_set_output_enabled()
587 dfll_writel(td, val, DFLL_OUTPUT_CFG); in dfll_pwm_set_output_enabled()
588 dfll_wmb(td); in dfll_pwm_set_output_enabled()
591 dfll_writel(td, val, DFLL_OUTPUT_CFG); in dfll_pwm_set_output_enabled()
592 dfll_wmb(td); in dfll_pwm_set_output_enabled()
594 ret = pinctrl_select_state(td->pwm_pin, td->pwm_disable_state); in dfll_pwm_set_output_enabled()
596 dev_warn(td->dev, "setting disable state failed\n"); in dfll_pwm_set_output_enabled()
598 val = dfll_readl(td, DFLL_OUTPUT_CFG); in dfll_pwm_set_output_enabled()
600 dfll_writel(td, val, DFLL_OUTPUT_CFG); in dfll_pwm_set_output_enabled()
601 dfll_wmb(td); in dfll_pwm_set_output_enabled()
615 static u32 dfll_set_force_output_value(struct tegra_dfll *td, u8 out_val) in dfll_set_force_output_value() argument
617 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE); in dfll_set_force_output_value()
620 dfll_writel(td, val, DFLL_OUTPUT_FORCE); in dfll_set_force_output_value()
621 dfll_wmb(td); in dfll_set_force_output_value()
623 return dfll_readl(td, DFLL_OUTPUT_FORCE); in dfll_set_force_output_value()
633 static void dfll_set_force_output_enabled(struct tegra_dfll *td, bool enable) in dfll_set_force_output_enabled() argument
635 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE); in dfll_set_force_output_enabled()
642 dfll_writel(td, val, DFLL_OUTPUT_FORCE); in dfll_set_force_output_enabled()
643 dfll_wmb(td); in dfll_set_force_output_enabled()
653 static int dfll_force_output(struct tegra_dfll *td, unsigned int out_sel) in dfll_force_output() argument
660 val = dfll_set_force_output_value(td, out_sel); in dfll_force_output()
661 if ((td->mode < DFLL_CLOSED_LOOP) && in dfll_force_output()
663 dfll_set_force_output_enabled(td, true); in dfll_force_output()
676 static void dfll_load_i2c_lut(struct tegra_dfll *td) in dfll_load_i2c_lut() argument
682 if (i < td->lut_min) in dfll_load_i2c_lut()
683 lut_index = td->lut_min; in dfll_load_i2c_lut()
684 else if (i > td->lut_max) in dfll_load_i2c_lut()
685 lut_index = td->lut_max; in dfll_load_i2c_lut()
689 val = regulator_list_hardware_vsel(td->vdd_reg, in dfll_load_i2c_lut()
690 td->lut[lut_index]); in dfll_load_i2c_lut()
691 __raw_writel(val, td->lut_base + i * 4); in dfll_load_i2c_lut()
694 dfll_i2c_wmb(td); in dfll_load_i2c_lut()
707 static void dfll_init_i2c_if(struct tegra_dfll *td) in dfll_init_i2c_if() argument
711 if (td->i2c_slave_addr > 0x7f) { in dfll_init_i2c_if()
712 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT; in dfll_init_i2c_if()
715 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT; in dfll_init_i2c_if()
719 dfll_i2c_writel(td, val, DFLL_I2C_CFG); in dfll_init_i2c_if()
721 dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR); in dfll_init_i2c_if()
723 val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8); in dfll_init_i2c_if()
729 __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR); in dfll_init_i2c_if()
730 dfll_i2c_wmb(td); in dfll_init_i2c_if()
741 static void dfll_init_out_if(struct tegra_dfll *td) in dfll_init_out_if() argument
745 td->lut_min = td->lut_bottom; in dfll_init_out_if()
746 td->lut_max = td->lut_size - 1; in dfll_init_out_if()
747 td->lut_safe = td->lut_min + (td->lut_min < td->lut_max ? 1 : 0); in dfll_init_out_if()
750 dfll_writel(td, 0, DFLL_OUTPUT_CFG); in dfll_init_out_if()
751 dfll_wmb(td); in dfll_init_out_if()
753 val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) | in dfll_init_out_if()
754 (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) | in dfll_init_out_if()
755 (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT); in dfll_init_out_if()
756 dfll_writel(td, val, DFLL_OUTPUT_CFG); in dfll_init_out_if()
757 dfll_wmb(td); in dfll_init_out_if()
759 dfll_writel(td, 0, DFLL_OUTPUT_FORCE); in dfll_init_out_if()
760 dfll_i2c_writel(td, 0, DFLL_INTR_EN); in dfll_init_out_if()
761 dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK, in dfll_init_out_if()
764 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) { in dfll_init_out_if()
765 u32 vinit = td->reg_init_uV; in dfll_init_out_if()
766 int vstep = td->soc->alignment.step_uv; in dfll_init_out_if()
767 unsigned long vmin = td->lut_uv[0]; in dfll_init_out_if()
774 dfll_force_output(td, vsel); in dfll_init_out_if()
777 dfll_load_i2c_lut(td); in dfll_init_out_if()
778 dfll_init_i2c_if(td); in dfll_init_out_if()
796 static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate) in find_lut_index_for_rate() argument
801 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); in find_lut_index_for_rate()
805 align_step = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv; in find_lut_index_for_rate()
808 for (i = td->lut_bottom; i < td->lut_size; i++) { in find_lut_index_for_rate()
809 if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_step) in find_lut_index_for_rate()
827 static int dfll_calculate_rate_request(struct tegra_dfll *td, in dfll_calculate_rate_request() argument
840 if (rate < td->dvco_rate_min) { in dfll_calculate_rate_request()
844 td->dvco_rate_min / 1000); in dfll_calculate_rate_request()
846 dev_err(td->dev, "%s: Rate %lu is too low\n", in dfll_calculate_rate_request()
851 rate = td->dvco_rate_min; in dfll_calculate_rate_request()
855 val = DVCO_RATE_TO_MULT(rate, td->ref_rate); in dfll_calculate_rate_request()
857 dev_err(td->dev, "%s: Rate %lu is above dfll range\n", in dfll_calculate_rate_request()
862 req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate); in dfll_calculate_rate_request()
865 req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate); in dfll_calculate_rate_request()
880 static void dfll_set_frequency_request(struct tegra_dfll *td, in dfll_set_frequency_request() argument
887 force_val = (req->lut_index - td->lut_safe) * coef / td->cg; in dfll_set_frequency_request()
896 dfll_writel(td, val, DFLL_FREQ_REQ); in dfll_set_frequency_request()
897 dfll_wmb(td); in dfll_set_frequency_request()
912 static int dfll_request_rate(struct tegra_dfll *td, unsigned long rate) in dfll_request_rate() argument
917 if (td->mode == DFLL_UNINITIALIZED) { in dfll_request_rate()
918 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n", in dfll_request_rate()
919 __func__, mode_name[td->mode]); in dfll_request_rate()
923 ret = dfll_calculate_rate_request(td, &req, rate); in dfll_request_rate()
927 td->last_unrounded_rate = rate; in dfll_request_rate()
928 td->last_req = req; in dfll_request_rate()
930 if (td->mode == DFLL_CLOSED_LOOP) in dfll_request_rate()
931 dfll_set_frequency_request(td, &td->last_req); in dfll_request_rate()
947 static int dfll_disable(struct tegra_dfll *td) in dfll_disable() argument
949 if (td->mode != DFLL_OPEN_LOOP) { in dfll_disable()
950 dev_err(td->dev, "cannot disable DFLL in %s mode\n", in dfll_disable()
951 mode_name[td->mode]); in dfll_disable()
955 dfll_set_mode(td, DFLL_DISABLED); in dfll_disable()
956 pm_runtime_put_sync(td->dev); in dfll_disable()
968 static int dfll_enable(struct tegra_dfll *td) in dfll_enable() argument
970 if (td->mode != DFLL_DISABLED) { in dfll_enable()
971 dev_err(td->dev, "cannot enable DFLL in %s mode\n", in dfll_enable()
972 mode_name[td->mode]); in dfll_enable()
976 pm_runtime_get_sync(td->dev); in dfll_enable()
977 dfll_set_mode(td, DFLL_OPEN_LOOP); in dfll_enable()
993 static void dfll_set_open_loop_config(struct tegra_dfll *td) in dfll_set_open_loop_config() argument
998 if (td->tune_range != DFLL_TUNE_LOW) in dfll_set_open_loop_config()
999 dfll_tune_low(td); in dfll_set_open_loop_config()
1001 val = dfll_readl(td, DFLL_FREQ_REQ); in dfll_set_open_loop_config()
1004 dfll_writel(td, val, DFLL_FREQ_REQ); in dfll_set_open_loop_config()
1005 dfll_wmb(td); in dfll_set_open_loop_config()
1016 static int dfll_lock(struct tegra_dfll *td) in dfll_lock() argument
1018 struct dfll_rate_req *req = &td->last_req; in dfll_lock()
1020 switch (td->mode) { in dfll_lock()
1026 dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n", in dfll_lock()
1031 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) in dfll_lock()
1032 dfll_pwm_set_output_enabled(td, true); in dfll_lock()
1034 dfll_i2c_set_output_enabled(td, true); in dfll_lock()
1036 dfll_set_mode(td, DFLL_CLOSED_LOOP); in dfll_lock()
1037 dfll_set_frequency_request(td, req); in dfll_lock()
1038 dfll_set_force_output_enabled(td, false); in dfll_lock()
1042 BUG_ON(td->mode > DFLL_CLOSED_LOOP); in dfll_lock()
1043 dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n", in dfll_lock()
1044 __func__, mode_name[td->mode]); in dfll_lock()
1056 static int dfll_unlock(struct tegra_dfll *td) in dfll_unlock() argument
1058 switch (td->mode) { in dfll_unlock()
1060 dfll_set_open_loop_config(td); in dfll_unlock()
1061 dfll_set_mode(td, DFLL_OPEN_LOOP); in dfll_unlock()
1062 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) in dfll_unlock()
1063 dfll_pwm_set_output_enabled(td, false); in dfll_unlock()
1065 dfll_i2c_set_output_enabled(td, false); in dfll_unlock()
1072 BUG_ON(td->mode > DFLL_CLOSED_LOOP); in dfll_unlock()
1073 dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n", in dfll_unlock()
1074 __func__, mode_name[td->mode]); in dfll_unlock()
1090 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_is_enabled() local
1092 return dfll_is_running(td); in dfll_clk_is_enabled()
1097 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_enable() local
1100 ret = dfll_enable(td); in dfll_clk_enable()
1104 ret = dfll_lock(td); in dfll_clk_enable()
1106 dfll_disable(td); in dfll_clk_enable()
1113 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_disable() local
1116 ret = dfll_unlock(td); in dfll_clk_disable()
1118 dfll_disable(td); in dfll_clk_disable()
1124 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_recalc_rate() local
1126 return td->last_unrounded_rate; in dfll_clk_recalc_rate()
1133 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_determine_rate() local
1137 ret = dfll_calculate_rate_request(td, &req, clk_req->rate); in dfll_clk_determine_rate()
1153 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_set_rate() local
1155 return dfll_request_rate(td, rate); in dfll_clk_set_rate()
1180 static int dfll_register_clk(struct tegra_dfll *td) in dfll_register_clk() argument
1184 dfll_clk_init_data.name = td->output_clock_name; in dfll_register_clk()
1185 td->dfll_clk_hw.init = &dfll_clk_init_data; in dfll_register_clk()
1187 td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw); in dfll_register_clk()
1188 if (IS_ERR(td->dfll_clk)) { in dfll_register_clk()
1189 dev_err(td->dev, "DFLL clock registration error\n"); in dfll_register_clk()
1193 ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get, in dfll_register_clk()
1194 td->dfll_clk); in dfll_register_clk()
1196 dev_err(td->dev, "of_clk_add_provider() failed\n"); in dfll_register_clk()
1198 clk_unregister(td->dfll_clk); in dfll_register_clk()
1212 static void dfll_unregister_clk(struct tegra_dfll *td) in dfll_unregister_clk() argument
1214 of_clk_del_provider(td->dev->of_node); in dfll_unregister_clk()
1215 clk_unregister(td->dfll_clk); in dfll_unregister_clk()
1216 td->dfll_clk = NULL; in dfll_unregister_clk()
1255 static u64 dfll_read_monitor_rate(struct tegra_dfll *td) in dfll_read_monitor_rate() argument
1260 if (!dfll_is_running(td)) in dfll_read_monitor_rate()
1263 v = dfll_readl(td, DFLL_MONITOR_DATA); in dfll_read_monitor_rate()
1265 pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate); in dfll_read_monitor_rate()
1267 s = dfll_readl(td, DFLL_FREQ_REQ); in dfll_read_monitor_rate()
1276 struct tegra_dfll *td = data; in attr_enable_get() local
1278 *val = dfll_is_running(td); in attr_enable_get()
1284 struct tegra_dfll *td = data; in attr_enable_set() local
1286 return val ? dfll_enable(td) : dfll_disable(td); in attr_enable_set()
1293 struct tegra_dfll *td = data; in attr_lock_get() local
1295 *val = (td->mode == DFLL_CLOSED_LOOP); in attr_lock_get()
1301 struct tegra_dfll *td = data; in attr_lock_set() local
1303 return val ? dfll_lock(td) : dfll_unlock(td); in attr_lock_set()
1309 struct tegra_dfll *td = data; in attr_rate_get() local
1311 *val = dfll_read_monitor_rate(td); in attr_rate_get()
1318 struct tegra_dfll *td = data; in attr_rate_set() local
1320 return dfll_request_rate(td, val); in attr_rate_set()
1327 struct tegra_dfll *td = s->private; in attr_registers_show() local
1332 val = dfll_i2c_readl(td, offs); in attr_registers_show()
1334 val = dfll_readl(td, offs); in attr_registers_show()
1341 dfll_i2c_readl(td, offs)); in attr_registers_show()
1344 dfll_i2c_readl(td, offs)); in attr_registers_show()
1346 if (td->pmu_if == TEGRA_DFLL_PMU_I2C) { in attr_registers_show()
1350 __raw_readl(td->i2c_controller_base + offs)); in attr_registers_show()
1355 __raw_readl(td->lut_base + offs)); in attr_registers_show()
1363 static void dfll_debug_init(struct tegra_dfll *td) in dfll_debug_init() argument
1367 if (!td || (td->mode == DFLL_UNINITIALIZED)) in dfll_debug_init()
1371 td->debugfs_dir = root; in dfll_debug_init()
1373 debugfs_create_file_unsafe("enable", 0644, root, td, in dfll_debug_init()
1375 debugfs_create_file_unsafe("lock", 0444, root, td, &lock_fops); in dfll_debug_init()
1376 debugfs_create_file_unsafe("rate", 0444, root, td, &rate_fops); in dfll_debug_init()
1377 debugfs_create_file("registers", 0444, root, td, &attr_registers_fops); in dfll_debug_init()
1381 static inline void dfll_debug_init(struct tegra_dfll *td) { } in dfll_debug_init() argument
1396 static void dfll_set_default_params(struct tegra_dfll *td) in dfll_set_default_params() argument
1400 val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32); in dfll_set_default_params()
1402 dfll_writel(td, val, DFLL_CONFIG); in dfll_set_default_params()
1404 val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) | in dfll_set_default_params()
1405 (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) | in dfll_set_default_params()
1406 (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) | in dfll_set_default_params()
1407 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) | in dfll_set_default_params()
1408 (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0); in dfll_set_default_params()
1409 dfll_writel(td, val, DFLL_PARAMS); in dfll_set_default_params()
1411 dfll_tune_low(td); in dfll_set_default_params()
1412 dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL); in dfll_set_default_params()
1413 dfll_writel(td, DFLL_MONITOR_CTRL_FREQ, DFLL_MONITOR_CTRL); in dfll_set_default_params()
1424 static int dfll_init_clks(struct tegra_dfll *td) in dfll_init_clks() argument
1426 td->ref_clk = devm_clk_get(td->dev, "ref"); in dfll_init_clks()
1427 if (IS_ERR(td->ref_clk)) { in dfll_init_clks()
1428 dev_err(td->dev, "missing ref clock\n"); in dfll_init_clks()
1429 return PTR_ERR(td->ref_clk); in dfll_init_clks()
1432 td->soc_clk = devm_clk_get(td->dev, "soc"); in dfll_init_clks()
1433 if (IS_ERR(td->soc_clk)) { in dfll_init_clks()
1434 dev_err(td->dev, "missing soc clock\n"); in dfll_init_clks()
1435 return PTR_ERR(td->soc_clk); in dfll_init_clks()
1438 td->i2c_clk = devm_clk_get(td->dev, "i2c"); in dfll_init_clks()
1439 if (IS_ERR(td->i2c_clk)) { in dfll_init_clks()
1440 dev_err(td->dev, "missing i2c clock\n"); in dfll_init_clks()
1441 return PTR_ERR(td->i2c_clk); in dfll_init_clks()
1443 td->i2c_clk_rate = clk_get_rate(td->i2c_clk); in dfll_init_clks()
1457 static int dfll_init(struct tegra_dfll *td) in dfll_init() argument
1461 td->ref_rate = clk_get_rate(td->ref_clk); in dfll_init()
1462 if (td->ref_rate != REF_CLOCK_RATE) { in dfll_init()
1463 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu", in dfll_init()
1464 td->ref_rate, REF_CLOCK_RATE); in dfll_init()
1468 reset_control_deassert(td->dfll_rst); in dfll_init()
1469 reset_control_deassert(td->dvco_rst); in dfll_init()
1471 ret = clk_prepare(td->ref_clk); in dfll_init()
1473 dev_err(td->dev, "failed to prepare ref_clk\n"); in dfll_init()
1477 ret = clk_prepare(td->soc_clk); in dfll_init()
1479 dev_err(td->dev, "failed to prepare soc_clk\n"); in dfll_init()
1483 ret = clk_prepare(td->i2c_clk); in dfll_init()
1485 dev_err(td->dev, "failed to prepare i2c_clk\n"); in dfll_init()
1489 td->last_unrounded_rate = 0; in dfll_init()
1491 pm_runtime_enable(td->dev); in dfll_init()
1492 pm_runtime_get_sync(td->dev); in dfll_init()
1494 dfll_set_mode(td, DFLL_DISABLED); in dfll_init()
1495 dfll_set_default_params(td); in dfll_init()
1497 if (td->soc->init_clock_trimmers) in dfll_init()
1498 td->soc->init_clock_trimmers(); in dfll_init()
1500 dfll_set_open_loop_config(td); in dfll_init()
1502 dfll_init_out_if(td); in dfll_init()
1504 pm_runtime_put_sync(td->dev); in dfll_init()
1509 clk_unprepare(td->soc_clk); in dfll_init()
1511 clk_unprepare(td->ref_clk); in dfll_init()
1513 reset_control_assert(td->dvco_rst); in dfll_init()
1514 reset_control_assert(td->dfll_rst); in dfll_init()
1528 struct tegra_dfll *td = dev_get_drvdata(dev); in tegra_dfll_suspend() local
1530 if (dfll_is_running(td)) { in tegra_dfll_suspend()
1531 dev_err(td->dev, "DFLL still enabled while suspending\n"); in tegra_dfll_suspend()
1535 reset_control_assert(td->dvco_rst); in tegra_dfll_suspend()
1536 reset_control_assert(td->dfll_rst); in tegra_dfll_suspend()
1553 struct tegra_dfll *td = dev_get_drvdata(dev); in tegra_dfll_resume() local
1555 reset_control_deassert(td->dfll_rst); in tegra_dfll_resume()
1556 reset_control_deassert(td->dvco_rst); in tegra_dfll_resume()
1558 pm_runtime_get_sync(td->dev); in tegra_dfll_resume()
1560 dfll_set_mode(td, DFLL_DISABLED); in tegra_dfll_resume()
1561 dfll_set_default_params(td); in tegra_dfll_resume()
1563 if (td->soc->init_clock_trimmers) in tegra_dfll_resume()
1564 td->soc->init_clock_trimmers(); in tegra_dfll_resume()
1566 dfll_set_open_loop_config(td); in tegra_dfll_resume()
1568 dfll_init_out_if(td); in tegra_dfll_resume()
1570 pm_runtime_put_sync(td->dev); in tegra_dfll_resume()
1584 static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV) in find_vdd_map_entry_exact() argument
1588 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM)) in find_vdd_map_entry_exact()
1591 align_step = uV / td->soc->alignment.step_uv; in find_vdd_map_entry_exact()
1592 n_voltages = regulator_count_voltages(td->vdd_reg); in find_vdd_map_entry_exact()
1594 reg_uV = regulator_list_voltage(td->vdd_reg, i); in find_vdd_map_entry_exact()
1598 reg_volt_id = reg_uV / td->soc->alignment.step_uv; in find_vdd_map_entry_exact()
1604 dev_err(td->dev, "no voltage map entry for %d uV\n", uV); in find_vdd_map_entry_exact()
1612 static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV) in find_vdd_map_entry_min() argument
1616 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM)) in find_vdd_map_entry_min()
1619 align_step = uV / td->soc->alignment.step_uv; in find_vdd_map_entry_min()
1620 n_voltages = regulator_count_voltages(td->vdd_reg); in find_vdd_map_entry_min()
1622 reg_uV = regulator_list_voltage(td->vdd_reg, i); in find_vdd_map_entry_min()
1626 reg_volt_id = reg_uV / td->soc->alignment.step_uv; in find_vdd_map_entry_min()
1632 dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV); in find_vdd_map_entry_min()
1645 static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max) in dfll_build_pwm_lut() argument
1650 int v_min = td->soc->cvb->min_millivolts * 1000; in dfll_build_pwm_lut()
1653 reg_volt = td->lut_uv[i]; in dfll_build_pwm_lut()
1660 td->lut[i] = i; in dfll_build_pwm_lut()
1666 td->lut_size = i; in dfll_build_pwm_lut()
1668 (lut_bottom + 1 >= td->lut_size)) { in dfll_build_pwm_lut()
1669 dev_err(td->dev, "no voltage above DFLL minimum %d mV\n", in dfll_build_pwm_lut()
1670 td->soc->cvb->min_millivolts); in dfll_build_pwm_lut()
1673 td->lut_bottom = lut_bottom; in dfll_build_pwm_lut()
1676 rate = get_dvco_rate_below(td, td->lut_bottom); in dfll_build_pwm_lut()
1678 dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n", in dfll_build_pwm_lut()
1679 td->soc->cvb->min_millivolts); in dfll_build_pwm_lut()
1682 td->dvco_rate_min = rate; in dfll_build_pwm_lut()
1700 static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max) in dfll_build_i2c_lut() argument
1706 v = td->soc->cvb->min_millivolts * 1000; in dfll_build_i2c_lut()
1707 lut = find_vdd_map_entry_exact(td, v); in dfll_build_i2c_lut()
1710 td->lut[0] = lut; in dfll_build_i2c_lut()
1711 td->lut_bottom = 0; in dfll_build_i2c_lut()
1716 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); in dfll_build_i2c_lut()
1721 if (v_opp <= td->soc->cvb->min_millivolts * 1000) in dfll_build_i2c_lut()
1722 td->dvco_rate_min = dev_pm_opp_get_freq(opp); in dfll_build_i2c_lut()
1731 selector = find_vdd_map_entry_min(td, v); in dfll_build_i2c_lut()
1734 if (selector != td->lut[j - 1]) in dfll_build_i2c_lut()
1735 td->lut[j++] = selector; in dfll_build_i2c_lut()
1739 selector = find_vdd_map_entry_exact(td, v); in dfll_build_i2c_lut()
1742 if (selector != td->lut[j - 1]) in dfll_build_i2c_lut()
1743 td->lut[j++] = selector; in dfll_build_i2c_lut()
1748 td->lut_size = j; in dfll_build_i2c_lut()
1750 if (!td->dvco_rate_min) in dfll_build_i2c_lut()
1751 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n", in dfll_build_i2c_lut()
1752 td->soc->cvb->min_millivolts); in dfll_build_i2c_lut()
1755 for (j = 0; j < td->lut_size; j++) in dfll_build_i2c_lut()
1756 td->lut_uv[j] = in dfll_build_i2c_lut()
1757 regulator_list_voltage(td->vdd_reg, in dfll_build_i2c_lut()
1758 td->lut[j]); in dfll_build_i2c_lut()
1765 static int dfll_build_lut(struct tegra_dfll *td) in dfll_build_lut() argument
1771 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate); in dfll_build_lut()
1773 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n"); in dfll_build_lut()
1779 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) in dfll_build_lut()
1780 return dfll_build_pwm_lut(td, v_max); in dfll_build_lut()
1782 return dfll_build_i2c_lut(td, v_max); in dfll_build_lut()
1795 static bool read_dt_param(struct tegra_dfll *td, const char *param, u32 *dest) in read_dt_param() argument
1797 int err = of_property_read_u32(td->dev->of_node, param, dest); in read_dt_param()
1800 dev_err(td->dev, "failed to read DT parameter %s: %d\n", in read_dt_param()
1816 static int dfll_fetch_i2c_params(struct tegra_dfll *td) in dfll_fetch_i2c_params() argument
1824 if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate)) in dfll_fetch_i2c_params()
1827 regmap = regulator_get_regmap(td->vdd_reg); in dfll_fetch_i2c_params()
1831 td->i2c_slave_addr = i2c_client->addr; in dfll_fetch_i2c_params()
1833 ret = regulator_get_hardware_vsel_register(td->vdd_reg, in dfll_fetch_i2c_params()
1837 dev_err(td->dev, in dfll_fetch_i2c_params()
1841 td->i2c_reg = vsel_reg; in dfll_fetch_i2c_params()
1846 static int dfll_fetch_pwm_params(struct tegra_dfll *td) in dfll_fetch_pwm_params() argument
1851 if (!td->soc->alignment.step_uv || !td->soc->alignment.offset_uv) { in dfll_fetch_pwm_params()
1852 dev_err(td->dev, in dfll_fetch_pwm_params()
1857 td->lut_uv[i] = td->soc->alignment.offset_uv + in dfll_fetch_pwm_params()
1858 i * td->soc->alignment.step_uv; in dfll_fetch_pwm_params()
1860 ret = read_dt_param(td, "nvidia,pwm-tristate-microvolts", in dfll_fetch_pwm_params()
1861 &td->reg_init_uV); in dfll_fetch_pwm_params()
1863 dev_err(td->dev, "couldn't get initialized voltage\n"); in dfll_fetch_pwm_params()
1867 ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period); in dfll_fetch_pwm_params()
1869 dev_err(td->dev, "couldn't get PWM period\n"); in dfll_fetch_pwm_params()
1872 td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1); in dfll_fetch_pwm_params()
1874 td->pwm_pin = devm_pinctrl_get(td->dev); in dfll_fetch_pwm_params()
1875 if (IS_ERR(td->pwm_pin)) { in dfll_fetch_pwm_params()
1876 dev_err(td->dev, "DT: missing pinctrl device\n"); in dfll_fetch_pwm_params()
1877 return PTR_ERR(td->pwm_pin); in dfll_fetch_pwm_params()
1880 td->pwm_enable_state = pinctrl_lookup_state(td->pwm_pin, in dfll_fetch_pwm_params()
1882 if (IS_ERR(td->pwm_enable_state)) { in dfll_fetch_pwm_params()
1883 dev_err(td->dev, "DT: missing pwm enabled state\n"); in dfll_fetch_pwm_params()
1884 return PTR_ERR(td->pwm_enable_state); in dfll_fetch_pwm_params()
1887 td->pwm_disable_state = pinctrl_lookup_state(td->pwm_pin, in dfll_fetch_pwm_params()
1889 if (IS_ERR(td->pwm_disable_state)) { in dfll_fetch_pwm_params()
1890 dev_err(td->dev, "DT: missing pwm disabled state\n"); in dfll_fetch_pwm_params()
1891 return PTR_ERR(td->pwm_disable_state); in dfll_fetch_pwm_params()
1904 static int dfll_fetch_common_params(struct tegra_dfll *td) in dfll_fetch_common_params() argument
1908 ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl); in dfll_fetch_common_params()
1909 ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate); in dfll_fetch_common_params()
1910 ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode); in dfll_fetch_common_params()
1911 ok &= read_dt_param(td, "nvidia,cf", &td->cf); in dfll_fetch_common_params()
1912 ok &= read_dt_param(td, "nvidia,ci", &td->ci); in dfll_fetch_common_params()
1913 ok &= read_dt_param(td, "nvidia,cg", &td->cg); in dfll_fetch_common_params()
1914 td->cg_scale = of_property_read_bool(td->dev->of_node, in dfll_fetch_common_params()
1917 if (of_property_read_string(td->dev->of_node, "clock-output-names", in dfll_fetch_common_params()
1918 &td->output_clock_name)) { in dfll_fetch_common_params()
1919 dev_err(td->dev, "missing clock-output-names property\n"); in dfll_fetch_common_params()
1943 struct tegra_dfll *td; in tegra_dfll_register() local
1951 td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL); in tegra_dfll_register()
1952 if (!td) in tegra_dfll_register()
1954 td->dev = &pdev->dev; in tegra_dfll_register()
1955 platform_set_drvdata(pdev, td); in tegra_dfll_register()
1957 td->soc = soc; in tegra_dfll_register()
1959 td->dfll_rst = devm_reset_control_get_optional(td->dev, "dfll"); in tegra_dfll_register()
1960 if (IS_ERR(td->dfll_rst)) { in tegra_dfll_register()
1961 dev_err(td->dev, "couldn't get dfll reset\n"); in tegra_dfll_register()
1962 return PTR_ERR(td->dfll_rst); in tegra_dfll_register()
1965 td->dvco_rst = devm_reset_control_get(td->dev, "dvco"); in tegra_dfll_register()
1966 if (IS_ERR(td->dvco_rst)) { in tegra_dfll_register()
1967 dev_err(td->dev, "couldn't get dvco reset\n"); in tegra_dfll_register()
1968 return PTR_ERR(td->dvco_rst); in tegra_dfll_register()
1971 ret = dfll_fetch_common_params(td); in tegra_dfll_register()
1973 dev_err(td->dev, "couldn't parse device tree parameters\n"); in tegra_dfll_register()
1977 if (of_property_read_bool(td->dev->of_node, "nvidia,pwm-to-pmic")) { in tegra_dfll_register()
1978 td->pmu_if = TEGRA_DFLL_PMU_PWM; in tegra_dfll_register()
1979 ret = dfll_fetch_pwm_params(td); in tegra_dfll_register()
1981 td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu"); in tegra_dfll_register()
1982 if (IS_ERR(td->vdd_reg)) { in tegra_dfll_register()
1983 dev_err(td->dev, "couldn't get vdd_cpu regulator\n"); in tegra_dfll_register()
1984 return PTR_ERR(td->vdd_reg); in tegra_dfll_register()
1986 td->pmu_if = TEGRA_DFLL_PMU_I2C; in tegra_dfll_register()
1987 ret = dfll_fetch_i2c_params(td); in tegra_dfll_register()
1992 ret = dfll_build_lut(td); in tegra_dfll_register()
1994 dev_err(td->dev, "couldn't build LUT\n"); in tegra_dfll_register()
2000 dev_err(td->dev, "no control register resource\n"); in tegra_dfll_register()
2004 td->base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
2005 if (!td->base) { in tegra_dfll_register()
2006 dev_err(td->dev, "couldn't ioremap DFLL control registers\n"); in tegra_dfll_register()
2012 dev_err(td->dev, "no i2c_base resource\n"); in tegra_dfll_register()
2016 td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
2017 if (!td->i2c_base) { in tegra_dfll_register()
2018 dev_err(td->dev, "couldn't ioremap i2c_base resource\n"); in tegra_dfll_register()
2024 dev_err(td->dev, "no i2c_controller_base resource\n"); in tegra_dfll_register()
2028 td->i2c_controller_base = devm_ioremap(td->dev, mem->start, in tegra_dfll_register()
2030 if (!td->i2c_controller_base) { in tegra_dfll_register()
2031 dev_err(td->dev, in tegra_dfll_register()
2038 dev_err(td->dev, "no lut_base resource\n"); in tegra_dfll_register()
2042 td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
2043 if (!td->lut_base) { in tegra_dfll_register()
2044 dev_err(td->dev, in tegra_dfll_register()
2049 ret = dfll_init_clks(td); in tegra_dfll_register()
2056 ret = dfll_init(td); in tegra_dfll_register()
2060 ret = dfll_register_clk(td); in tegra_dfll_register()
2066 dfll_debug_init(td); in tegra_dfll_register()
2082 struct tegra_dfll *td = platform_get_drvdata(pdev); in tegra_dfll_unregister() local
2088 if (td->mode != DFLL_DISABLED) { in tegra_dfll_unregister()
2094 debugfs_remove_recursive(td->debugfs_dir); in tegra_dfll_unregister()
2096 dfll_unregister_clk(td); in tegra_dfll_unregister()
2099 clk_unprepare(td->ref_clk); in tegra_dfll_unregister()
2100 clk_unprepare(td->soc_clk); in tegra_dfll_unregister()
2101 clk_unprepare(td->i2c_clk); in tegra_dfll_unregister()
2103 reset_control_assert(td->dvco_rst); in tegra_dfll_unregister()
2104 reset_control_assert(td->dfll_rst); in tegra_dfll_unregister()
2106 return td->soc; in tegra_dfll_unregister()