50 static struct clk *clk[clk_max];  variable
55 	clk[dummy] = imx_clk_fixed("dummy", 0);  in _mx31_clocks_init()
56 	clk[ckih] = imx_clk_fixed("ckih", fref);  in _mx31_clocks_init()
57 	clk[ckil] = imx_clk_fixed("ckil", 32768);  in _mx31_clocks_init()
58 	clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL);  in _mx31_clocks_init()
59 	clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL);  in _mx31_clocks_init()
60 	clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL);  in _mx31_clocks_init()
61 …clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_…  in _mx31_clocks_init()
62 	clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3);  in _mx31_clocks_init()
63 	clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);  in _mx31_clocks_init()
64 	clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3);  in _mx31_clocks_init()
65 	clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);  in _mx31_clocks_init()
66 	clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5);  in _mx31_clocks_init()
67 	clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));  in _mx31_clocks_init()
68 	clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel));  in _mx31_clocks_init()
69 	clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel));  in _mx31_clocks_init()
70 	clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9);  in _mx31_clocks_init()
71 	clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2);  in _mx31_clocks_init()
72 	clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3);  in _mx31_clocks_init()
73 	clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3);  in _mx31_clocks_init()
74 	clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6);  in _mx31_clocks_init()
75 	clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0);  in _mx31_clocks_init()
76 	clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2);  in _mx31_clocks_init()
77 	clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4);  in _mx31_clocks_init()
78 	clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6);  in _mx31_clocks_init()
79 	clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8);  in _mx31_clocks_init()
80 	clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10);  in _mx31_clocks_init()
81 	clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12);  in _mx31_clocks_init()
82 	clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14);  in _mx31_clocks_init()
83 	clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16);  in _mx31_clocks_init()
84 	clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18);  in _mx31_clocks_init()
85 	clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20);  in _mx31_clocks_init()
86 	clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22);  in _mx31_clocks_init()
87 	clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24);  in _mx31_clocks_init()
88 	clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26);  in _mx31_clocks_init()
89 	clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28);  in _mx31_clocks_init()
90 	clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30);  in _mx31_clocks_init()
91 	clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0);  in _mx31_clocks_init()
92 	clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2);  in _mx31_clocks_init()
93 	clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4);  in _mx31_clocks_init()
94 	clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6);  in _mx31_clocks_init()
95 	clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8);  in _mx31_clocks_init()
96 	clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10);  in _mx31_clocks_init()
97 	clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12);  in _mx31_clocks_init()
98 	clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14);  in _mx31_clocks_init()
99 	clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16);  in _mx31_clocks_init()
100 	clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18);  in _mx31_clocks_init()
101 	clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20);  in _mx31_clocks_init()
102 	clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22);  in _mx31_clocks_init()
103 	clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24);  in _mx31_clocks_init()
104 	clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26);  in _mx31_clocks_init()
105 	clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28);  in _mx31_clocks_init()
106 	clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30);  in _mx31_clocks_init()
107 	clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0);  in _mx31_clocks_init()
108 	clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2);  in _mx31_clocks_init()
109 	clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4);  in _mx31_clocks_init()
110 	clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6);  in _mx31_clocks_init()
111 	clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8);  in _mx31_clocks_init()
112 	clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);  in _mx31_clocks_init()
113 	clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);  in _mx31_clocks_init()
115 	imx_check_clocks(clk, ARRAY_SIZE(clk));  in _mx31_clocks_init()
117 	clk_set_parent(clk[csi], clk[upll]);  in _mx31_clocks_init()
118 	clk_prepare_enable(clk[emi_gate]);  in _mx31_clocks_init()
119 	clk_prepare_enable(clk[iim_gate]);  in _mx31_clocks_init()
121 	clk_disable_unprepare(clk[iim_gate]);  in _mx31_clocks_init()
146 	clk_data.clks = clk;  in mx31_clocks_init_dt()
147 	clk_data.clk_num = ARRAY_SIZE(clk);  in mx31_clocks_init_dt()