132 	struct hisi_clock_data *clk_data;  in hi3516cv300_clk_register()  local
135 	clk_data = hisi_clk_alloc(pdev, HI3516CV300_CRG_NR_CLKS);  in hi3516cv300_clk_register()
136 	if (!clk_data)  in hi3516cv300_clk_register()
140 			ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);  in hi3516cv300_clk_register()
145 			ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);  in hi3516cv300_clk_register()
150 			ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);  in hi3516cv300_clk_register()
155 			of_clk_src_onecell_get, &clk_data->clk_data);  in hi3516cv300_clk_register()
159 	return clk_data;  in hi3516cv300_clk_register()
163 				ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);  in hi3516cv300_clk_register()
166 			ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);  in hi3516cv300_clk_register()
169 			ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);  in hi3516cv300_clk_register()
180 			ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data);  in hi3516cv300_clk_unregister()
182 			ARRAY_SIZE(hi3516cv300_mux_clks), crg->clk_data);  in hi3516cv300_clk_unregister()
184 			ARRAY_SIZE(hi3516cv300_fixed_rate_clks), crg->clk_data);  in hi3516cv300_clk_unregister()
206 	struct hisi_clock_data *clk_data;  in hi3516cv300_sysctrl_clk_register()  local
209 	clk_data = hisi_clk_alloc(pdev, HI3516CV300_SYSCTRL_NR_CLKS);  in hi3516cv300_sysctrl_clk_register()
210 	if (!clk_data)  in hi3516cv300_sysctrl_clk_register()
214 			ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);  in hi3516cv300_sysctrl_clk_register()
220 			of_clk_src_onecell_get, &clk_data->clk_data);  in hi3516cv300_sysctrl_clk_register()
224 	return clk_data;  in hi3516cv300_sysctrl_clk_register()
228 			ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);  in hi3516cv300_sysctrl_clk_register()
240 			crg->clk_data);  in hi3516cv300_sysctrl_clk_unregister()
277 	crg->clk_data = crg->funcs->register_clks(pdev);  in hi3516cv300_crg_probe()
278 	if (IS_ERR(crg->clk_data)) {  in hi3516cv300_crg_probe()
280 		return PTR_ERR(crg->clk_data);  in hi3516cv300_crg_probe()