clk-hi6220.c - OpenGrok cross reference for /linux-6.6.21/drivers/clk/hisilicon/clk-hi6220.c

Lines Matching refs:__initdata
22 static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
38 static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = {
51 static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
91 static const char *mmc0_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
92 static const char *mmc0_mux1_p[] __initdata = { "mmc0_mux0", "pll_media_gate", };
93 static const char *mmc0_src_p[] __initdata = { "mmc0srcsel", "mmc0_div", };
94 static const char *mmc1_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
95 static const char *mmc1_mux1_p[] __initdata = { "mmc1_mux0", "pll_media_gate", };
96 static const char *mmc1_src_p[]  __initdata = { "mmc1srcsel", "mmc1_div", };
97 static const char *mmc2_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
98 static const char *mmc2_mux1_p[] __initdata = { "mmc2_mux0", "pll_media_gate", };
99 static const char *mmc2_src_p[]  __initdata = { "mmc2srcsel", "mmc2_div", };
100 static const char *mmc0_sample_in[] __initdata = { "mmc0_sample", "mmc0_pad", };
101 static const char *mmc1_sample_in[] __initdata = { "mmc1_sample", "mmc1_pad", };
102 static const char *mmc2_sample_in[] __initdata = { "mmc2_sample", "mmc2_pad", };
103 static const char *uart1_src[] __initdata = { "clk_tcxo", "clk_150m", };
104 static const char *uart2_src[] __initdata = { "clk_tcxo", "clk_150m", };
105 static const char *uart3_src[] __initdata = { "clk_tcxo", "clk_150m", };
106 static const char *uart4_src[] __initdata = { "clk_tcxo", "clk_150m", };
107 static const char *hifi_src[] __initdata = { "syspll", "pll_media_gate", };
109 static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = {
146 static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {
166 static struct hi6220_divider_clock hi6220_div_clks_sys[] __initdata = {
198 static const char *clk_1000_1200_src[] __initdata = { "pll_gpu_gate", "media_syspll_src", };
199 static const char *clk_1440_1200_src[] __initdata = { "media_syspll_src", "media_pll_src", };
200 static const char *clk_1000_1440_src[] __initdata = { "pll_gpu_gate", "media_pll_src", };
202 static struct hisi_gate_clock hi6220_separated_gate_clks_media[] __initdata = {
218 static struct hisi_mux_clock hi6220_mux_clks_media[] __initdata = {
224 static struct hi6220_divider_clock hi6220_div_clks_media[] __initdata = {
255 static struct hisi_gate_clock hi6220_gate_clks_power[] __initdata = {
263 static struct hi6220_divider_clock hi6220_div_clks_power[] __initdata = {