445 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_enable()  local
449 	if (pclk->lock)  in xgene_clk_enable()
450 		spin_lock_irqsave(pclk->lock, flags);  in xgene_clk_enable()
452 	if (pclk->param.csr_reg) {  in xgene_clk_enable()
455 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_enable()
456 					pclk->param.reg_clk_offset);  in xgene_clk_enable()
457 		data |= pclk->param.reg_clk_mask;  in xgene_clk_enable()
458 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_enable()
459 					pclk->param.reg_clk_offset);  in xgene_clk_enable()
462 			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,  in xgene_clk_enable()
466 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_enable()
467 					pclk->param.reg_csr_offset);  in xgene_clk_enable()
468 		data &= ~pclk->param.reg_csr_mask;  in xgene_clk_enable()
469 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_enable()
470 					pclk->param.reg_csr_offset);  in xgene_clk_enable()
473 			pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,  in xgene_clk_enable()
477 	if (pclk->lock)  in xgene_clk_enable()
478 		spin_unlock_irqrestore(pclk->lock, flags);  in xgene_clk_enable()
485 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_disable()  local
489 	if (pclk->lock)  in xgene_clk_disable()
490 		spin_lock_irqsave(pclk->lock, flags);  in xgene_clk_disable()
492 	if (pclk->param.csr_reg) {  in xgene_clk_disable()
495 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_disable()
496 					pclk->param.reg_csr_offset);  in xgene_clk_disable()
497 		data |= pclk->param.reg_csr_mask;  in xgene_clk_disable()
498 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_disable()
499 					pclk->param.reg_csr_offset);  in xgene_clk_disable()
502 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_disable()
503 					pclk->param.reg_clk_offset);  in xgene_clk_disable()
504 		data &= ~pclk->param.reg_clk_mask;  in xgene_clk_disable()
505 		xgene_clk_write(data, pclk->param.csr_reg +  in xgene_clk_disable()
506 					pclk->param.reg_clk_offset);  in xgene_clk_disable()
509 	if (pclk->lock)  in xgene_clk_disable()
510 		spin_unlock_irqrestore(pclk->lock, flags);  in xgene_clk_disable()
515 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_is_enabled()  local
518 	if (pclk->param.csr_reg) {  in xgene_clk_is_enabled()
520 		data = xgene_clk_read(pclk->param.csr_reg +  in xgene_clk_is_enabled()
521 					pclk->param.reg_clk_offset);  in xgene_clk_is_enabled()
523 			data & pclk->param.reg_clk_mask ? "enabled" :  in xgene_clk_is_enabled()
529 	return data & pclk->param.reg_clk_mask ? 1 : 0;  in xgene_clk_is_enabled()
535 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_recalc_rate()  local
538 	if (pclk->param.divider_reg) {  in xgene_clk_recalc_rate()
539 		data = xgene_clk_read(pclk->param.divider_reg +  in xgene_clk_recalc_rate()
540 					pclk->param.reg_divider_offset);  in xgene_clk_recalc_rate()
541 		data >>= pclk->param.reg_divider_shift;  in xgene_clk_recalc_rate()
542 		data &= (1 << pclk->param.reg_divider_width) - 1;  in xgene_clk_recalc_rate()
559 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_set_rate()  local
565 	if (pclk->lock)  in xgene_clk_set_rate()
566 		spin_lock_irqsave(pclk->lock, flags);  in xgene_clk_set_rate()
568 	if (pclk->param.divider_reg) {  in xgene_clk_set_rate()
573 		divider &= (1 << pclk->param.reg_divider_width) - 1;  in xgene_clk_set_rate()
574 		divider <<= pclk->param.reg_divider_shift;  in xgene_clk_set_rate()
577 		data = xgene_clk_read(pclk->param.divider_reg +  in xgene_clk_set_rate()
578 				pclk->param.reg_divider_offset);  in xgene_clk_set_rate()
579 		data &= ~(((1 << pclk->param.reg_divider_width) - 1)  in xgene_clk_set_rate()
580 				<< pclk->param.reg_divider_shift);  in xgene_clk_set_rate()
582 		xgene_clk_write(data, pclk->param.divider_reg +  in xgene_clk_set_rate()
583 					pclk->param.reg_divider_offset);  in xgene_clk_set_rate()
590 	if (pclk->lock)  in xgene_clk_set_rate()
591 		spin_unlock_irqrestore(pclk->lock, flags);  in xgene_clk_set_rate()
599 	struct xgene_clk *pclk = to_xgene_clk(hw);  in xgene_clk_round_rate()  local
603 	if (pclk->param.divider_reg) {  in xgene_clk_round_rate()