Lines Matching refs:GENMASK_ULL
96 #define IVPU_MMU_EVT_OP_MASK GENMASK_ULL(7, 0)
97 #define IVPU_MMU_EVT_SSID_MASK GENMASK_ULL(31, 12)
100 #define IVPU_MMU_Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)
102 #define IVPU_MMU_STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)
126 #define IVPU_MMU_CMDQ_OP GENMASK_ULL(7, 0)
128 #define IVPU_MMU_CD_0_TCR_T0SZ GENMASK_ULL(5, 0)
129 #define IVPU_MMU_CD_0_TCR_TG0 GENMASK_ULL(7, 6)
130 #define IVPU_MMU_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8)
131 #define IVPU_MMU_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10)
132 #define IVPU_MMU_CD_0_TCR_SH0 GENMASK_ULL(13, 12)
137 #define IVPU_MMU_CD_0_TCR_IPS GENMASK_ULL(34, 32)
144 #define IVPU_MMU_CD_0_ASID GENMASK_ULL(63, 48)
156 #define IVPU_MMU_CD_1_TTB0_MASK GENMASK_ULL(51, 4)
158 #define IVPU_MMU_STE_0_S1CDMAX GENMASK_ULL(63, 59)
159 #define IVPU_MMU_STE_0_S1FMT GENMASK_ULL(5, 4)
163 #define IVPU_MMU_STE_0_CFG GENMASK_ULL(3, 1)
164 #define IVPU_MMU_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)
168 #define IVPU_MMU_STE_1_CONT GENMASK_ULL(16, 13)
169 #define IVPU_MMU_STE_1_STRW GENMASK_ULL(31, 30)
170 #define IVPU_MMU_STE_1_PRIVCFG GENMASK_ULL(49, 48)
172 #define IVPU_MMU_STE_1_INSTCFG GENMASK_ULL(51, 50)
180 #define IVPU_MMU_STE_1_S1CIR GENMASK_ULL(3, 2)
181 #define IVPU_MMU_STE_1_S1COR GENMASK_ULL(5, 4)
182 #define IVPU_MMU_STE_1_S1CSH GENMASK_ULL(7, 6)
183 #define IVPU_MMU_STE_1_S1DSS GENMASK_ULL(1, 0)