Lines Matching defs:asic_fixed_properties
693 struct asic_fixed_properties { struct
694 struct hw_queue_properties *hw_queues_props;
695 struct hl_special_block_info *special_blocks;
696 struct hl_skip_blocks_cfg skip_special_blocks_cfg;
697 struct cpucp_info cpucp_info;
698 char uboot_ver[VERSION_MAX_LEN];
699 char preboot_ver[VERSION_MAX_LEN];
700 struct hl_mmu_properties dmmu;
701 struct hl_mmu_properties pmmu;
702 struct hl_mmu_properties pmmu_huge;
703 struct hl_hints_range hints_dram_reserved_va_range;
704 struct hl_hints_range hints_host_reserved_va_range;
705 struct hl_hints_range hints_host_hpage_reserved_va_range;
706 u64 sram_base_address;
707 u64 sram_end_address;
708 u64 sram_user_base_address;
709 u64 dram_base_address;
710 u64 dram_end_address;
711 u64 dram_user_base_address;
712 u64 dram_size;
713 u64 dram_pci_bar_size;
714 u64 max_power_default;
715 u64 dc_power_default;
716 u64 dram_size_for_default_page_mapping;
717 u64 pcie_dbi_base_address;
718 u64 pcie_aux_dbi_reg_addr;
719 u64 mmu_pgt_addr;
720 u64 mmu_dram_default_page_addr;
721 u64 tpc_enabled_mask;
722 u64 tpc_binning_mask;
723 u64 dram_enabled_mask;
724 u64 dram_binning_mask;
725 u64 dram_hints_align_mask;
726 u64 cfg_base_address;
727 u64 mmu_cache_mng_addr;
728 u64 mmu_cache_mng_size;
729 u64 device_dma_offset_for_host_access;
730 u64 host_base_address;
731 u64 host_end_address;
732 u64 max_freq_value;
733 u64 engine_core_interrupt_reg_addr;
734 u32 clk_pll_index;
735 u32 mmu_pgt_size;
736 u32 mmu_pte_size;
737 u32 mmu_hop_table_size;
738 u32 mmu_hop0_tables_total_size;
739 u32 dram_page_size;
740 u32 cfg_size;
741 u32 sram_size;
742 u32 max_asid;
743 u32 num_of_events;
744 u32 psoc_pci_pll_nr;
745 u32 psoc_pci_pll_nf;
746 u32 psoc_pci_pll_od;
747 u32 psoc_pci_pll_div_factor;
748 u32 psoc_timestamp_frequency;
749 u32 high_pll;
750 u32 cb_pool_cb_cnt;
751 u32 cb_pool_cb_size;
752 u32 decoder_enabled_mask;
753 u32 decoder_binning_mask;
754 u32 rotator_enabled_mask;
755 u32 edma_enabled_mask;
756 u32 edma_binning_mask;
757 u32 max_pending_cs;
758 u32 max_queues;
759 u32 fw_preboot_cpu_boot_dev_sts0;
760 u32 fw_preboot_cpu_boot_dev_sts1;
761 u32 fw_bootfit_cpu_boot_dev_sts0;
762 u32 fw_bootfit_cpu_boot_dev_sts1;
763 u32 fw_app_cpu_boot_dev_sts0;
764 u32 fw_app_cpu_boot_dev_sts1;
765 u32 max_dec;
766 u32 hmmu_hif_enabled_mask;
767 u32 faulty_dram_cluster_map;
768 u32 xbar_edge_enabled_mask;
769 u32 device_mem_alloc_default_page_size;
770 u32 num_engine_cores;
771 u32 max_num_of_engines;
772 u32 num_of_special_blocks;
773 u32 glbl_err_cause_num;
774 u32 hbw_flush_reg;
775 u16 collective_first_sob;
776 u16 collective_first_mon;
777 u16 sync_stream_first_sob;
778 u16 sync_stream_first_mon;
779 u16 first_available_user_sob[HL_MAX_DCORES];
780 u16 first_available_user_mon[HL_MAX_DCORES];
781 u16 first_available_user_interrupt;
782 u16 first_available_cq[HL_MAX_DCORES];
783 u16 user_interrupt_count;
784 u16 user_dec_intr_count;
785 u16 tpc_interrupt_id;
786 u16 eq_interrupt_id;
787 u16 cache_line_size;
788 u16 server_type;
789 u8 completion_queues_count;
790 u8 completion_mode;
791 u8 mme_master_slave_mode;
792 u8 fw_security_enabled;
793 u8 fw_cpu_boot_dev_sts0_valid;
794 u8 fw_cpu_boot_dev_sts1_valid;
795 u8 dram_supports_virtual_memory;
796 u8 hard_reset_done_by_fw;
797 u8 num_functional_hbms;
798 u8 hints_range_reservation;
799 u8 iatu_done_by_fw;
800 u8 dynamic_fw_load;
801 u8 gic_interrupts_enable;
802 u8 use_get_power_for_reset_history;
803 u8 supports_compute_reset;
804 u8 allow_inference_soft_reset;
805 u8 configurable_stop_on_err;
806 u8 set_max_power_on_device_init;
807 u8 supports_user_set_page_size;
808 u8 dma_mask;
809 u8 supports_advanced_cpucp_rc;
810 u8 supports_engine_modes;