249 	if (hwc->idx == UNCORE_PMC_IDX_FIXED)  in nhmex_uncore_msr_enable_event()
371 	reg1->idx = 0;  in nhmex_bbox_hw_config()
383 	if (reg1->idx != EXTRA_REG_NONE) {  in nhmex_bbox_msr_enable_event()
456 	reg1->idx = 0;  in nhmex_sbox_hw_config()
468 	if (reg1->idx != EXTRA_REG_NONE) {  in nhmex_sbox_msr_enable_event()
553 static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box, int idx, u64 config)  in nhmex_mbox_get_shared_reg()  argument
560 	if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {  in nhmex_mbox_get_shared_reg()
561 		er = &box->shared_regs[idx];  in nhmex_mbox_get_shared_reg()
577 	idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;  in nhmex_mbox_get_shared_reg()
578 	if (WARN_ON_ONCE(idx >= 4))  in nhmex_mbox_get_shared_reg()
590 	if (__BITS_VALUE(atomic_read(&er->ref), idx, 8)) {  in nhmex_mbox_get_shared_reg()
592 			mask |= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);  in nhmex_mbox_get_shared_reg()
594 			mask |= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);  in nhmex_mbox_get_shared_reg()
598 		atomic_add(1 << (idx * 8), &er->ref);  in nhmex_mbox_get_shared_reg()
601 				NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);  in nhmex_mbox_get_shared_reg()
604 				WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);  in nhmex_mbox_get_shared_reg()
614 static void nhmex_mbox_put_shared_reg(struct intel_uncore_box *box, int idx)  in nhmex_mbox_put_shared_reg()  argument
618 	if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {  in nhmex_mbox_put_shared_reg()
619 		er = &box->shared_regs[idx];  in nhmex_mbox_put_shared_reg()
624 	idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;  in nhmex_mbox_put_shared_reg()
626 	atomic_sub(1 << (idx * 8), &er->ref);  in nhmex_mbox_put_shared_reg()
633 	u64 idx, orig_idx = __BITS_VALUE(reg1->idx, 0, 8);  in nhmex_mbox_alter_er()  local
637 	idx = orig_idx - EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;  in nhmex_mbox_alter_er()
639 		config &= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);  in nhmex_mbox_alter_er()
641 		config &= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);  in nhmex_mbox_alter_er()
643 		idx = new_idx - orig_idx;  in nhmex_mbox_alter_er()
644 		config <<= 3 * idx;  in nhmex_mbox_alter_er()
646 		idx = orig_idx - new_idx;  in nhmex_mbox_alter_er()
647 		config >>= 3 * idx;  in nhmex_mbox_alter_er()
659 			hwc->config += idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;  in nhmex_mbox_alter_er()
661 			hwc->config -= idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;  in nhmex_mbox_alter_er()
663 		reg1->idx = ~0xff | new_idx;  in nhmex_mbox_alter_er()
673 	int i, idx[2], alloc = 0;  in nhmex_mbox_get_constraint()  local
676 	idx[0] = __BITS_VALUE(reg1->idx, 0, 8);  in nhmex_mbox_get_constraint()
677 	idx[1] = __BITS_VALUE(reg1->idx, 1, 8);  in nhmex_mbox_get_constraint()
681 			idx[i] = 0xff;  in nhmex_mbox_get_constraint()
683 		if (idx[i] == 0xff)  in nhmex_mbox_get_constraint()
686 		if (!nhmex_mbox_get_shared_reg(box, idx[i],  in nhmex_mbox_get_constraint()
693 	if (reg2->idx != EXTRA_REG_NONE &&  in nhmex_mbox_get_constraint()
695 	    !nhmex_mbox_get_shared_reg(box, reg2->idx, reg2->config))  in nhmex_mbox_get_constraint()
705 		if (idx[0] != 0xff && idx[0] != __BITS_VALUE(reg1->idx, 0, 8))  in nhmex_mbox_get_constraint()
706 			nhmex_mbox_alter_er(event, idx[0], true);  in nhmex_mbox_get_constraint()
708 		if (reg2->idx != EXTRA_REG_NONE)  in nhmex_mbox_get_constraint()
713 	if (idx[0] != 0xff && !(alloc & 0x1) &&  in nhmex_mbox_get_constraint()
714 	    idx[0] >= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {  in nhmex_mbox_get_constraint()
721 		BUG_ON(__BITS_VALUE(reg1->idx, 1, 8) != 0xff);  in nhmex_mbox_get_constraint()
722 		idx[0] -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;  in nhmex_mbox_get_constraint()
723 		idx[0] = (idx[0] + 1) % 4;  in nhmex_mbox_get_constraint()
724 		idx[0] += EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;  in nhmex_mbox_get_constraint()
725 		if (idx[0] != __BITS_VALUE(reg1->idx, 0, 8)) {  in nhmex_mbox_get_constraint()
726 			config1 = nhmex_mbox_alter_er(event, idx[0], false);  in nhmex_mbox_get_constraint()
732 		nhmex_mbox_put_shared_reg(box, idx[0]);  in nhmex_mbox_get_constraint()
734 		nhmex_mbox_put_shared_reg(box, idx[1]);  in nhmex_mbox_get_constraint()
747 		nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 0, 8));  in nhmex_mbox_put_constraint()
749 		nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 1, 8));  in nhmex_mbox_put_constraint()
753 		nhmex_mbox_put_shared_reg(box, reg2->idx);  in nhmex_mbox_put_constraint()
760 	if (er->idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)  in nhmex_mbox_extra_reg_idx()
761 		return er->idx;  in nhmex_mbox_extra_reg_idx()
762 	return er->idx + (er->event >> NHMEX_M_PMON_CTL_INC_SEL_SHIFT) - 0xd;  in nhmex_mbox_extra_reg_idx()
785 		if (WARN_ON_ONCE(msr >= 0xffff || er->idx >= 0xff))  in nhmex_mbox_hw_config()
789 		if (er->idx == EXTRA_REG_NHMEX_M_PLD)  in nhmex_mbox_hw_config()
794 		reg1->idx &= ~(0xff << (reg_idx * 8));  in nhmex_mbox_hw_config()
796 		reg1->idx |= nhmex_mbox_extra_reg_idx(er) << (reg_idx * 8);  in nhmex_mbox_hw_config()
806 		reg2->idx = EXTRA_REG_NHMEX_M_FILTER;  in nhmex_mbox_hw_config()
819 static u64 nhmex_mbox_shared_reg_config(struct intel_uncore_box *box, int idx)  in nhmex_mbox_shared_reg_config()  argument
825 	if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)  in nhmex_mbox_shared_reg_config()
826 		return box->shared_regs[idx].config;  in nhmex_mbox_shared_reg_config()
840 	int idx;  in nhmex_mbox_msr_enable_event()  local
842 	idx = __BITS_VALUE(reg1->idx, 0, 8);  in nhmex_mbox_msr_enable_event()
843 	if (idx != 0xff)  in nhmex_mbox_msr_enable_event()
845 			nhmex_mbox_shared_reg_config(box, idx));  in nhmex_mbox_msr_enable_event()
846 	idx = __BITS_VALUE(reg1->idx, 1, 8);  in nhmex_mbox_msr_enable_event()
847 	if (idx != 0xff)  in nhmex_mbox_msr_enable_event()
849 			nhmex_mbox_shared_reg_config(box, idx));  in nhmex_mbox_msr_enable_event()
851 	if (reg2->idx != EXTRA_REG_NONE) {  in nhmex_mbox_msr_enable_event()
950 	if (reg1->idx % 2) {  in nhmex_rbox_alter_er()
951 		reg1->idx--;  in nhmex_rbox_alter_er()
954 		reg1->idx++;  in nhmex_rbox_alter_er()
959 	switch (reg1->idx % 6) {  in nhmex_rbox_alter_er()
985 	int idx, er_idx;  in nhmex_rbox_get_constraint()  local
992 	idx = reg1->idx % 6;  in nhmex_rbox_get_constraint()
995 	er_idx = idx;  in nhmex_rbox_get_constraint()
999 	er_idx += (reg1->idx / 6) * 5;  in nhmex_rbox_get_constraint()
1003 	if (idx < 2) {  in nhmex_rbox_get_constraint()
1009 	} else if (idx == 2 || idx == 3) {  in nhmex_rbox_get_constraint()
1014 		u64 mask = 0xff << ((idx - 2) * 8);  in nhmex_rbox_get_constraint()
1015 		if (!__BITS_VALUE(atomic_read(&er->ref), idx - 2, 8) ||  in nhmex_rbox_get_constraint()
1017 			atomic_add(1 << ((idx - 2) * 8), &er->ref);  in nhmex_rbox_get_constraint()
1043 		idx ^= 1;  in nhmex_rbox_get_constraint()
1044 		if (idx != reg1->idx % 6) {  in nhmex_rbox_get_constraint()
1045 			if (idx == 2)  in nhmex_rbox_get_constraint()
1047 			else if (idx == 3)  in nhmex_rbox_get_constraint()
1053 			if (idx != reg1->idx % 6)  in nhmex_rbox_get_constraint()
1066 	int idx, er_idx;  in nhmex_rbox_put_constraint()  local
1071 	idx = reg1->idx % 6;  in nhmex_rbox_put_constraint()
1072 	er_idx = idx;  in nhmex_rbox_put_constraint()
1075 	er_idx += (reg1->idx / 6) * 5;  in nhmex_rbox_put_constraint()
1078 	if (idx == 2 || idx == 3)  in nhmex_rbox_put_constraint()
1079 		atomic_sub(1 << ((idx - 2) * 8), &er->ref);  in nhmex_rbox_put_constraint()
1091 	int idx;  in nhmex_rbox_hw_config()  local
1093 	idx = (event->hw.config & NHMEX_R_PMON_CTL_EV_SEL_MASK) >>  in nhmex_rbox_hw_config()
1095 	if (idx >= 0x18)  in nhmex_rbox_hw_config()
1098 	reg1->idx = idx;  in nhmex_rbox_hw_config()
1101 	switch (idx % 6) {  in nhmex_rbox_hw_config()
1116 	int idx, port;  in nhmex_rbox_msr_enable_event()  local
1118 	idx = reg1->idx;  in nhmex_rbox_msr_enable_event()
1119 	port = idx / 6 + box->pmu->pmu_idx * 4;  in nhmex_rbox_msr_enable_event()
1121 	switch (idx % 6) {  in nhmex_rbox_msr_enable_event()
1131 			uncore_shared_reg_config(box, 2 + (idx / 6) * 5));  in nhmex_rbox_msr_enable_event()