30 	unsigned int mask = 1 << hw_cpu;  in rcpm_v1_irq_mask()  local
32 	setbits32(&rcpm_v1_regs->cpmimr, mask);  in rcpm_v1_irq_mask()
33 	setbits32(&rcpm_v1_regs->cpmcimr, mask);  in rcpm_v1_irq_mask()
34 	setbits32(&rcpm_v1_regs->cpmmcmr, mask);  in rcpm_v1_irq_mask()
35 	setbits32(&rcpm_v1_regs->cpmnmimr, mask);  in rcpm_v1_irq_mask()
41 	unsigned int mask = 1 << hw_cpu;  in rcpm_v2_irq_mask()  local
43 	setbits32(&rcpm_v2_regs->tpmimr0, mask);  in rcpm_v2_irq_mask()
44 	setbits32(&rcpm_v2_regs->tpmcimr0, mask);  in rcpm_v2_irq_mask()
45 	setbits32(&rcpm_v2_regs->tpmmcmr0, mask);  in rcpm_v2_irq_mask()
46 	setbits32(&rcpm_v2_regs->tpmnmimr0, mask);  in rcpm_v2_irq_mask()
52 	unsigned int mask = 1 << hw_cpu;  in rcpm_v1_irq_unmask()  local
54 	clrbits32(&rcpm_v1_regs->cpmimr, mask);  in rcpm_v1_irq_unmask()
55 	clrbits32(&rcpm_v1_regs->cpmcimr, mask);  in rcpm_v1_irq_unmask()
56 	clrbits32(&rcpm_v1_regs->cpmmcmr, mask);  in rcpm_v1_irq_unmask()
57 	clrbits32(&rcpm_v1_regs->cpmnmimr, mask);  in rcpm_v1_irq_unmask()
63 	unsigned int mask = 1 << hw_cpu;  in rcpm_v2_irq_unmask()  local
65 	clrbits32(&rcpm_v2_regs->tpmimr0, mask);  in rcpm_v2_irq_unmask()
66 	clrbits32(&rcpm_v2_regs->tpmcimr0, mask);  in rcpm_v2_irq_unmask()
67 	clrbits32(&rcpm_v2_regs->tpmmcmr0, mask);  in rcpm_v2_irq_unmask()
68 	clrbits32(&rcpm_v2_regs->tpmnmimr0, mask);  in rcpm_v2_irq_unmask()
71 static void rcpm_v1_set_ip_power(bool enable, u32 mask)  in rcpm_v1_set_ip_power()  argument
74 		setbits32(&rcpm_v1_regs->ippdexpcr, mask);  in rcpm_v1_set_ip_power()
76 		clrbits32(&rcpm_v1_regs->ippdexpcr, mask);  in rcpm_v1_set_ip_power()
79 static void rcpm_v2_set_ip_power(bool enable, u32 mask)  in rcpm_v2_set_ip_power()  argument
82 		setbits32(&rcpm_v2_regs->ippdexpcr[0], mask);  in rcpm_v2_set_ip_power()
84 		clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask);  in rcpm_v2_set_ip_power()
90 	unsigned int mask = 1 << hw_cpu;  in rcpm_v1_cpu_enter_state()  local
94 		setbits32(&rcpm_v1_regs->cdozcr, mask);  in rcpm_v1_cpu_enter_state()
97 		setbits32(&rcpm_v1_regs->cnapcr, mask);  in rcpm_v1_cpu_enter_state()
108 	u32 mask = 1 << cpu_core_index_of_thread(cpu);  in rcpm_v2_cpu_enter_state()  local
116 		setbits32(&rcpm_v2_regs->pcph15setr, mask);  in rcpm_v2_cpu_enter_state()
119 		setbits32(&rcpm_v2_regs->pcph20setr, mask);  in rcpm_v2_cpu_enter_state()
122 		setbits32(&rcpm_v2_regs->pcph30setr, mask);  in rcpm_v2_cpu_enter_state()
167 	unsigned int mask = 1 << hw_cpu;  in rcpm_v1_cpu_exit_state()  local
171 		clrbits32(&rcpm_v1_regs->cdozcr, mask);  in rcpm_v1_cpu_exit_state()
174 		clrbits32(&rcpm_v1_regs->cnapcr, mask);  in rcpm_v1_cpu_exit_state()
191 	u32 mask = 1 << cpu_core_index_of_thread(cpu);  in rcpm_v2_cpu_exit_state()  local
198 		setbits32(&rcpm_v2_regs->pcph15clrr, mask);  in rcpm_v2_cpu_exit_state()
201 		setbits32(&rcpm_v2_regs->pcph20clrr, mask);  in rcpm_v2_cpu_exit_state()
204 		setbits32(&rcpm_v2_regs->pcph30clrr, mask);  in rcpm_v2_cpu_exit_state()
286 	static u32 mask;  in rcpm_common_freeze_time_base()  local
289 		mask = in_be32(tben_reg);  in rcpm_common_freeze_time_base()
290 		clrbits32(tben_reg, mask);  in rcpm_common_freeze_time_base()
292 		setbits32(tben_reg, mask);  in rcpm_common_freeze_time_base()