Lines Matching refs:li
62 li r24,0 /* CPU number */
110 li r0,0
155 li r4, 0 /* higer 32bit */
204 li r3,0
220 li r0,0
358 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
389 li r13,0
459 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
488 li r13,0
530 li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
536 li r10,0xf85 /* Mask to apply from PTE */
575 li r12,0 /* MMUCR = 0 */
602 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
611 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
613 li r12,0
676 li r12,0 /* MMUCR = 0 */
690 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
698 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
700 li r12,0
756 li r10,0xf85 /* Mask to apply from PTE */
795 li r3,MachineCheckA@l
868 li r4,0 /* Start at TLB entry 0 */
869 li r3,0 /* Set PAGEID inval value */
902 li r4, 0 /* Load the kernel physical address */
906 li r0,0
911 li r5,0
925 li r5,0
928 li r0,63 /* TLB slot 63 */
946 li r6,0
963 li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G)
964 li r0,62 /* TLB slot 0 */
1015 li r0,0
1028 li r0,0
1069 li r5,0
1114 li r0,0
1125 li r5,0
1177 li r5,(PPC47x_TLB2_S_RW | PPC47x_TLB2_IMG)