Lines Matching refs:uint
19 uint sc_siumcr;
20 uint sc_sypcr;
21 uint sc_swt;
24 uint sc_sipend;
25 uint sc_simask;
26 uint sc_siel;
27 uint sc_sivec;
28 uint sc_tesr;
30 uint sc_sdcr;
37 uint pcmc_pbr0;
38 uint pcmc_por0;
39 uint pcmc_pbr1;
40 uint pcmc_por1;
41 uint pcmc_pbr2;
42 uint pcmc_por2;
43 uint pcmc_pbr3;
44 uint pcmc_por3;
45 uint pcmc_pbr4;
46 uint pcmc_por4;
47 uint pcmc_pbr5;
48 uint pcmc_por5;
49 uint pcmc_pbr6;
50 uint pcmc_por6;
51 uint pcmc_pbr7;
52 uint pcmc_por7;
54 uint pcmc_pgcra;
55 uint pcmc_pgcrb;
56 uint pcmc_pscr;
58 uint pcmc_pipr;
60 uint pcmc_per;
67 uint memc_br0;
68 uint memc_or0;
69 uint memc_br1;
70 uint memc_or1;
71 uint memc_br2;
72 uint memc_or2;
73 uint memc_br3;
74 uint memc_or3;
75 uint memc_br4;
76 uint memc_or4;
77 uint memc_br5;
78 uint memc_or5;
79 uint memc_br6;
80 uint memc_or6;
81 uint memc_br7;
82 uint memc_or7;
84 uint memc_mar;
85 uint memc_mcr;
87 uint memc_mamr;
88 uint memc_mbmr;
91 uint memc_mdr;
152 uint sit_tbreff0;
153 uint sit_tbreff1;
157 uint sit_rtc;
158 uint sit_rtsec;
159 uint sit_rtcal;
163 uint sit_pitc;
164 uint sit_pitr;
194 uint car_sccr;
195 uint car_plprcr;
196 uint car_rsr;
203 uint sitk_tbscrk;
204 uint sitk_tbreff0k;
205 uint sitk_tbreff1k;
206 uint sitk_tbk;
208 uint sitk_rtcsck;
209 uint sitk_rtck;
210 uint sitk_rtseck;
211 uint sitk_rtcalk;
213 uint sitk_piscrk;
214 uint sitk_pitck;
221 uint cark_sccrk;
222 uint cark_plprcrk;
223 uint cark_rsrk;
240 uint vid_vbcb;
241 uint res4;
242 uint vid_vfcr0;
243 uint vid_vfaa0;
244 uint vid_vfba0;
245 uint vid_vfcr1;
246 uint vid_vfaa1;
247 uint vid_vfba1;
254 uint lcd_lccr;
255 uint lcd_lchcr;
256 uint lcd_lcvcr;
258 uint lcd_lcfaa;
259 uint lcd_lcfba;
285 uint sdma_sdar;
305 uint cpic_cicr;
306 uint cpic_cipr;
307 uint cpic_cimr;
308 uint cpic_cisr;
329 uint utmode;
364 uint scc_gsmrl;
365 uint scc_gsmrh;
393 uint fec_addr_low; /* lower 32 bits of station address */
396 uint fec_grp_hash_table_high; /* upper 32-bits of hash table */
397 uint fec_grp_hash_table_low; /* lower 32-bits of hash table */
398 uint fec_r_des_start; /* beginning of Rx descriptor ring */
399 uint fec_x_des_start; /* beginning of Tx descriptor ring */
400 uint fec_r_buff_size; /* Rx buffer size */
401 uint res2[9]; /* reserved */
402 uint fec_ecntrl; /* ethernet control register */
403 uint fec_ievent; /* interrupt event register */
404 uint fec_imask; /* interrupt mask register */
405 uint fec_ivec; /* interrupt level and vector status */
406 uint fec_r_des_active; /* Rx ring updated flag */
407 uint fec_x_des_active; /* Tx ring updated flag */
408 uint res3[10]; /* reserved */
409 uint fec_mii_data; /* MII data register */
410 uint fec_mii_speed; /* MII speed control register */
411 uint res4[17]; /* reserved */
412 uint fec_r_bound; /* end of RAM (read-only) */
413 uint fec_r_fstart; /* Rx FIFO start address */
414 uint res5[6]; /* reserved */
415 uint fec_x_fstart; /* Tx FIFO start address */
416 uint res6[17]; /* reserved */
417 uint fec_fun_code; /* fec SDMA function code */
418 uint res7[3]; /* reserved */
419 uint fec_r_cntrl; /* Rx control register */
420 uint fec_r_hash; /* Rx hash register */
421 uint res8[14]; /* reserved */
422 uint fec_x_cntrl; /* Tx control register */
423 uint res9[0x1e]; /* reserved */
455 uint cp_brgc1;
456 uint cp_brgc2;
457 uint cp_brgc3;
458 uint cp_brgc4;
485 uint cp_pbdir;
486 uint cp_pbpar;
489 uint cp_pbdat;
493 uint cp_pedir;
494 uint cp_pepar;
495 uint cp_peso;
496 uint cp_peodr;
497 uint cp_pedat;
502 uint cp_cptr;
506 uint cp_simode;
512 uint cp_sicr;
513 uint cp_sirp;